G35 datasheet(8/351 Pages) INTEL

8 / 351 page

Datasheet

8.1.6

CC—Class Code..................................................................... 229

8.1.7

CLS—Cache Line Size............................................................. 230

8.1.8

MLT2—Master Latency Timer................................................... 230

8.1.9

HDR2—Header Type .............................................................. 231

8.1.10

GMADR—Graphics Memory Range Address ................................ 231

8.1.11

IOBAR—I/O Base Address....................................................... 232

8.1.12

SVID2—Subsystem Vendor Identification .................................. 232

8.1.13

SID2—Subsystem Identification .............................................. 233

8.1.14

ROMADR—Video BIOS ROM Base Address ................................. 233

8.1.15

CAPPOINT—Capabilities Pointer ............................................... 234

8.1.16

INTRLINE—Interrupt Line ....................................................... 234

8.1.17

INTRPIN—Interrupt Pin .......................................................... 234

8.1.18

MINGNT—Minimum Grant ....................................................... 235

8.1.19

MAXLAT—Maximum Latency ................................................... 235

8.1.20

MCAPPTR—Mirror of Dev 0 Capabilities Pointer .......................... 236

8.1.21

CAPID0—Mirror of Dev0 Capability Identifier ............................. 236

8.1.22

MGGC— Mirror of Dev0 GMCH Graphics Control Register ............. 237

8.1.23

DEVEN—Mirror of Dev0 Device Enable ...................................... 238

8.1.24

SSRW—Software Scratch Read Write........................................ 239

8.1.25

BSM—Base of Stolen Memory.................................................. 239

8.1.26

HSRW—Hardware Scratch Read Write ...................................... 240

8.1.27

MSI_CAPID— Message Signaled Interrupts Capability ID ............. 240

8.1.28

MC—Message Control............................................................. 241

8.1.29

MA—Message Address............................................................ 242

8.1.30

MD—Message Data ................................................................ 242

8.1.31

GDRST—Graphics Debug Reset ............................................... 243

8.1.32

PMCAPID—Power Management Capabilities ID ........................... 244

8.1.33

PMCAP—Power Management Capabilities .................................. 244

8.1.34

PMCS—Power Management Control/Status................................ 245

8.1.35

SWSMI—Software SMI ........................................................... 246

8.2

IGD Configuration Register Details (D2:F1) ............................................ 247

8.2.1

VID2—Vendor Identification .................................................... 249

8.2.2

DID2—Device Identification .................................................... 249

8.2.3

PCICMD2—PCI Command ....................................................... 250

8.2.4

PCISTS2—PCI Status ............................................................. 251

8.2.5

RID2—Revision Identification .................................................. 252

8.2.6

CC—Class Code Register ........................................................ 252

8.2.7

CLS—Cache Line Size............................................................. 253

8.2.8

MLT2—Master Latency Timer................................................... 253

8.2.9

HDR2—Header Type .............................................................. 254

8.2.10

MMADR—Memory Mapped Range Address ................................. 254

8.2.11

SVID2—Subsystem Vendor Identification .................................. 255

8.2.12

SID2—Subsystem Identification .............................................. 255

8.2.13

ROMADR—Video BIOS ROM Base Address ................................. 256

8.2.14

CAPPOINT—Capabilities Pointer ............................................... 256

8.2.15

MINGNT—Minimum Grant ....................................................... 257

8.2.16

MAXLAT—Maximum Latency ................................................... 257

8.2.17

MCAPPTR—Mirror of Dev 0 Capabilities Pointer .......................... 257

8.2.18

CAPID0—Capability Identifier .................................................. 258

8.2.19

MGGC—Mirror of Dev 0 GMCH Graphics Control Register ............. 259

8.2.20

DEVEN—Device Enable........................................................... 260

8.2.21

SSRW—Mirror of Func0 Software Scratch Read Write.................. 261

8.2.22

BSM—Mirror of Func0 Base of Stolen Memory............................ 262

8.2.23

HSRW—Mirror of Dev2 Func0 Hardware Scratch Read Write ........ 262

8.2.24

GDRST—Mirror of Dev2 Func0 Graphics Reset ........................... 263

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