G35 datasheet(4/351 Pages) INTEL

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Datasheet

3.3.4

High BIOS Area.......................................................................54

3.4

Main Memory Address Space (4 GB to TOUUD) .........................................55

3.4.1

Memory Re-claim Background ...................................................56

3.4.2

Memory Reclaiming .................................................................56

3.5

PCI Express* Configuration Address Space...............................................56

3.6

PCI Express* Graphics Attach (PEG)........................................................57

3.7

Graphics Memory Address Ranges...........................................................58

3.8

System Management Mode (SMM) ..........................................................58

3.8.1

SMM Space Definition ..............................................................59

3.8.2

SMM Space Restrictions............................................................59

3.8.3

SMM Space Combinations .........................................................60

3.8.4

SMM Control Combinations .......................................................60

3.8.5

SMM Space Decode and Transaction Handling..............................61

3.8.6

Processor WB Transaction to an Enabled SMM Address Space ........61

3.8.7

SMM Access Through GTT TLB...................................................61

3.9

Memory Shadowing ..............................................................................62

3.10

I/O Address Space................................................................................62

3.10.1

PCI Express* I/O Address Mapping ............................................63

3.11

MCH Decode Rules and Cross-Bridge Address Mapping...............................63

3.11.1

Legacy VGA and I/O Range Decode Rules ...................................64

GMCH Register Description ...............................................................................66

4.1

4.2

Configuration Process and Registers........................................................68

4.2.1

Platform Configuration Structure ...............................................68

4.3

Configuration Mechanisms .....................................................................69

4.3.1

Standard PCI Configuration Mechanism ......................................69

4.3.2

PCI Express* Enhanced Configuration Mechanism ........................70

4.4

Routing Configuration Accesses ..............................................................71

4.4.1

Internal Device Configuration Accesses.......................................72

4.4.2

Bridge Related Configuration Accesses........................................73

4.5

I/O Mapped Registers ...........................................................................74

4.5.1

CONFIG_ADDRESS—Configuration Address Register.....................74

4.5.2

CONFIG_DATA—Configuration Data Register ...............................76

DRAM Controller Registers (D0:F0)....................................................................78

5.1

DRAM Controller (D0:F0).......................................................................78

5.1.1

VID—Vendor Identification........................................................80

5.1.2

DID—Device Identification ........................................................80

5.1.3

PCICMD—PCI Command...........................................................81

5.1.4

PCISTS—PCI Status .................................................................82

5.1.5

RID—Revision Identification......................................................83

5.1.6

CC—Class Code.......................................................................84

5.1.7

MLT—Master Latency Timer ......................................................84

5.1.8

HDR—Header Type ..................................................................85

5.1.9

SVID—Subsystem Vendor Identification......................................85

5.1.10

SID—Subsystem Identification ..................................................85

5.1.11

CAPPTR—Capabilities Pointer ....................................................86

5.1.12

PXPEPBAR—PCI Express* Egress Port Base Address .....................86

5.1.13

MCHBAR—GMCH Memory Mapped Register Range Base ................87

5.1.14

GGC—GMCH Graphics Control ...................................................88

5.1.15

DEVEN—Device Enable.............................................................89

5.1.16

PCIEXBAR—PCI Express* Register Range Base Address ................90

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