G35 datasheet(6/351 Pages) INTEL

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Datasheet

5.2.32

EPC0DRB3— ME Channel 0 DRAM Rank Boundary Address 3........ 141

5.2.33

EPC0DRA01—ME Channel 0 DRAM Rank 0,1 Attribute ................. 142

5.2.34

EPC0DRA23—ME Channel 0 DRAM Rank 2,3 Attribute ................. 142

5.2.35

EPDCYCTRKWRTPRE—EPD CYCTRK WRT PRE............................. 143

5.2.36

EPDCYCTRKWRTACT—EPD CYCTRK WRT ACT ............................ 143

5.2.37

EPDCYCTRKWRTWR—EPD CYCTRK WRT WR .............................. 144

5.2.38

EPDCYCTRKWRTRD—EPD CYCTRK WRT READ............................ 144

5.2.39

EPDCKECONFIGREG—EPD CKE Related Configuration Register ..... 145

5.2.40

MEMEMSPACE—ME Memory Space Configuration ....................... 147

5.2.41

EPDREFCONFIG—EP DRAM Refresh Configuration....................... 148

5.2.42

TSC1—Thermal Sensor Control 1 ............................................. 150

5.2.43

TSC2—Thermal Sensor Control 2 ............................................. 151

5.2.44

TSS—Thermal Sensor Status................................................... 152

5.2.45

TSTTP—Thermal Sensor Temperature Trip Point......................... 152

5.2.46

TCO—Thermal Calibration Offset.............................................. 153

5.2.47

THERM1—Hardware Throttle Control ........................................ 154

5.2.48

TIS—Thermal Interrupt Status ................................................ 154

5.2.49

TSMICMD—Thermal SMI Command.......................................... 156

5.2.50

PMSTS—Power Management Status ......................................... 157

5.3

MPBAR.............................................................................................. 158

5.3.1

EPESD—EP Element Self Description ........................................ 158

5.3.2

EPLE1D—Controller Link Entry 1 Description.............................. 159

5.3.3

EPLE1A— Controller Link Entry 1 Address ................................. 159

5.3.4

EPLE2D— Controller Link Entry 2 Description............................. 160

5.3.5

EPLE2A—EP Link Entry 2 Address ............................................ 161

PCI Express* Registers (D1:F0) ...................................................................... 162

6.1

PCI Express* Configuration Register Details (D1:F0) ............................... 165

6.1.1

VID1—Vendor Identification .................................................... 165

6.1.2

DID1—Device Identification .................................................... 165

6.1.3

PCICMD1—PCI Command ....................................................... 166

6.1.4

PCISTS1—PCI Status ............................................................. 168

6.1.5

RID1—Revision Identification .................................................. 169

6.1.6

CC1—Class Code ................................................................... 169

6.1.7

CL1—Cache Line Size............................................................. 170

6.1.8

HDR1—Header Type .............................................................. 170

6.1.9

PBUSN1—Primary Bus Number................................................ 170

6.1.10

SBUSN1—Secondary Bus Number............................................ 171

6.1.11

SUBUSN1—Subordinate Bus Number........................................ 171

6.1.12

IOBASE1—I/O Base Address ................................................... 172

6.1.13

IOLIMIT1—I/O Limit Address................................................... 172

6.1.14

SSTS1—Secondary Status ...................................................... 173

6.1.15

MBASE1—Memory Base Address.............................................. 174

6.1.16

MLIMIT1—Memory Limit Address ............................................. 175

6.1.17

PMBASE1—Prefetchable Memory Base Address .......................... 176

6.1.18

PMLIMIT1—Prefetchable Memory Limit Address.......................... 177

6.1.19

PMBASEU1—Prefetchable Memory Base Address ........................ 178

6.1.20

PMLIMITU1—Prefetchable Memory Limit Address........................ 179

6.1.21

CAPPTR1—Capabilities Pointer................................................. 180

6.1.22

INTRLINE1—Interrupt Line...................................................... 180

6.1.23

INTRPIN1—Interrupt Pin......................................................... 180

6.1.24

BCTRL1—Bridge Control ......................................................... 181

6.1.25

PM_CAPID1—Power Management Capabilities............................ 183

6.1.26

PM_CS1—Power Management Control/Status ............................ 184

6.1.27

SS_CAPID—Subsystem ID and Vendor ID Capabilities ................ 185

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