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MSP430F5259 Datasheet(PDF) 16 Page - Texas Instruments

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Part # MSP430F5259
Description  MSP430F525x Mixed Signal Microcontroller
PDF  107 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430F5259 Datasheet(HTML) 16 Page - Texas Instruments

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Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
SR/CG1/R2
Constant Generator
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R15
General-Purpose Register
R14
MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903A – MAY 2013 – REVISED JULY 2013
www.ti.com
Short-Form Description
CPU (Link to user's guide)
The MSP430 CPU has a 16-bit RISC architecture
that is highly transparent to the application. All
operations, other than program-flow instructions, are
performed as register operations in conjunction with
seven addressing modes for source operand and four
addressing modes for destination operand.
The CPU is integrated with 16 registers that provide
reduced instruction execution time. The register-to-
register operation execution time is one cycle of the
CPU clock.
Four of the registers, R0 to R3, are dedicated as
program counter, stack pointer, status register, and
constant
generator,
respectively.
The
remaining
registers are general-purpose registers.
Peripherals are connected to the CPU using data,
address, and control buses and can be handled with
all instructions.
The instruction set consists of the original 51
instructions with three formats and seven address
modes and additional instructions for the expanded
address range. Each instruction can operate on word
and byte data.
Operating Modes
The MSP430 has one active mode and six software selectable low-power modes of operation. An interrupt event
can wake up the device from any of the low-power modes, service the request, and restore back to the low-
power mode on return from the interrupt program.
The following seven operating modes can be configured by software:
•
Low-power mode 3 (LPM3)
•
Active mode (AM)
–
CPU is disabled
–
All clocks are active
–
MCLK, FLL loop control, and DCOCLK are
•
Low-power mode 0 (LPM0)
disabled
–
CPU is disabled
–
DCO's dc generator is disabled
–
ACLK and SMCLK remain active, MCLK is
–
ACLK remains active
disabled
•
Low-power mode 4 (LPM4)
–
FLL loop control remains active
–
CPU is disabled
•
Low-power mode 1 (LPM1)
–
ACLK is disabled
–
CPU is disabled
–
MCLK, FLL loop control, and DCOCLK are
–
FLL loop control is disabled
disabled
–
ACLK and SMCLK remain active, MCLK is
–
DCO's dc generator is disabled
disabled
–
Crystal oscillator is stopped
•
Low-power mode 2 (LPM2)
–
Complete data retention
–
CPU is disabled
•
Low-power mode 4.5 (LPM4.5)
–
MCLK and FLL loop control and DCOCLK are
–
Internal regulator disabled
disabled
–
No data retention
–
DCO's dc-generator remains enabled
–
Wakeup from RST/NMI, P1, and P2
–
ACLK remains active
16
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Copyright © 2013, Texas Instruments Incorporated



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