MSP430F5259 datasheet(66/107 Pages) TI1

66 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note

(1), Figure 16 and Figure 17)

PARAMETER

TEST CONDITIONS

VCC

VIO

MIN

MAX

UNIT

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tSTE,LEAD

STE lead time, STE low to clock

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

STE lag time, Last clock to STE

tSTE,LAG

high

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

STE access time, STE low to SOMI

tSTE,ACC

data out

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

STE disable time, STE high to

tSTE,DIS

SOMI high impedance

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tSU,SI

SIMO input data setup time

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tHD,SI

SIMO input data hold time

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

UCLK edge to SOMI valid,

1.8 V

1.62 V to 1.80 V

CL = 20 pF,

3.0 V

1.62 V to 1.98 V

PMMCOREV = 0

tVALID,SO

SOMI output data valid time(2)

UCLK edge to SOMI valid,

2.4 V

1.62 V to 1.98 V

CL = 20 pF,

3.0 V

1.62 V to 1.98 V

PMMCOREV = 3

1.8 V

1.62 V to 1.80 V

CL = 20 pF,

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tHD,SO

SOMI output data hold time(3)

2.4 V

1.62 V to 1.98 V

CL = 20 pF,

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(Master) + tSU,SI(USCI), tSU,MI(Master) + tVALID,SO(USCI)).

For the master's parameters tSU,MI(Master) and tVALID,MO(Master) see the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SOMI output after the output changing UCLK clock edge. See the timing diagrams

in Figure 16 and Figure 17.

(3)

Specifies how long data on the SOMI output is valid after the output changing UCLK clock edge. See the timing diagrams in Figure 16

and Figure 17.

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MSP430F5259 Datasheet(PDF) 66 Page - Texas Instruments

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