MSP430F5259 datasheet(48/107 Pages) TI1

48 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1) (2)

-40 °C

25 °C

60 °C

85°C

PARAMETER

VCC

PMMCOREVx

UNIT

TYP

MAX

TYP

MAX

TYP

MAX

TYP

MAX

2.2 V

103

ILPM0,1MHz

Low-power mode 0(3) (4)

µA

3.0 V

105

101

112

124

2.2 V

6.7

10.6

ILPM2

Low-power mode 2(5) (4)

µA

3.0 V

7.2

11.6

1.8

2.1

3.4

8.4

2.2 V

1.9

2.2

3.6

8.7

2.0

2.4

3.8

9.0

Low-power mode 3, crystal

ILPM3,XT1LF

2.0

2.3

3.1

3.6

8.6

µA

mode(6) (4)

2.1

2.5

3.8

8.9

3.0 V

2.2

2.6

3.9

9.2

2.3

2.7

4.1

4.0

9.2

1.3

1.6

2.9

2.6

8.5

1.3

1.6

2.8

8.8

Low-power mode 3,

ILPM3,VLO

3.0 V

µA

VLO mode(7) (4)

1.4

1.7

2.9

9.2

1.5

1.8

3.2

2.9

9.2

1.1

1.3

1.7

2.6

7.5

1.3

1.4

2.7

7.7

ILPM4

Low-power mode 4(8) (4)

3.0 V

µA

1.4

2.8

7.9

1.5

1.8

2.8

7.9

ILPM4.5

Low-power mode 4.5(9)

3.0 V

0.15

0.18

0.35

0.26

0.5

1.0

µA

Current supplied from

DVIO while

DVCC = AVCC = 0 V,

IDVIO_START

DVIO = 1.62 V to 1.98 V,

0 V

1.40

2.0

1.45

1.5

2.1

µA

All DVIO I/O floating

including BSLEN and

RST/NMI

(1)

All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2)

The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load

capacitance are chosen to closely match the required 12.5 pF.

(3)

Current for the watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz

(4)

Current for brownout and high-side supervisor (SVSH) normal mode included. Low-side supervisor (SVSL) and low-side monitor (SVML)

disabled. High-side monitor (SVMH) disabled. RAM retention enabled.

(5)

Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1

MHz operation, DCO bias generator enabled.)

(6)

Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz

(7)

Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz

(8)

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

(9)

Internal regulator disabled. No data retention.

CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK = fMCLK = fSMCLK = 0 MHz

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