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MSP430F5259 Datasheet(PDF) 22 Page - Texas Instruments

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Part # MSP430F5259
Description  MSP430F525x Mixed Signal Microcontroller
PDF  107 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430F5259 Datasheet(HTML) 22 Page - Texas Instruments

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903A – MAY 2013 – REVISED JULY 2013
www.ti.com
Spy-Bi-Wire Interface
In addition to the standard JTAG interface, the MSP430 family supports the two wire Spy-Bi-Wire interface. Spy-
Bi-Wire can be used to interface with MSP430 development tools and device programmers. The Spy-Bi-Wire
interface pin requirements are shown inTable 10. For further details on interfacing to development tools and
device programmers, see the MSP430™ Hardware Tools User's Guide (SLAU278). For a complete description
of the features of the JTAG interface and its implementation, see MSP430™ Programming Via the JTAG
Interface (SLAU320). Additional information can be found in Designing with MSP430F522x and MSP430F521x
Devices (SLAA558).
Table 10. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
DIRECTION
FUNCTION
TEST/SBWTCK
IN
Spy-Bi-Wire clock input
RSTDVCC/SBWTDIO
IN, OUT
Spy-Bi-Wire data input/output
DVCC, AVCC
Device power supply
DVIO
I/O power supply
DVSS
Ground supply
NOTE
Traditionally, on other MSP430 devices, the RST/NMI pin is used for SBWTDIO, so care
must be taken not to mistakenly use the incorrect pin. On the F525x series of devices, it is
required to use RSTDVCC for SBWTDIO as shown in Table 10. Additional information can
be found in Designing with MSP430F522x and MSP430F521x Devices (SLAA558).
Flash Memory (Link to user's guide)
The flash memory can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the
CPU. The CPU can perform single-byte, single-word, and long-word writes to the flash memory. Features of the
flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
128 bytes each. Each segment in main memory is 512 bytes in size.
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
•
Segments A to D can be erased individually. Segments A to D are also calledinformation memory.
•
Segment A can be locked separately.
RAM Memory (Link to user's guide)
The RAM memory is made up of n sectors. Each sector can be completely powered down to reduce leakage;
however, all data is lost during power down. Features of the RAM memory include:
•
RAM memory has n sectors. The sizes of the sectors can be found inMemory Organization.
•
Each sector 0 to n can be complete disabled; however, all data in a sector is lost when it is disabled.
•
Each sector 0 to n automatically enters low-power retention mode when possible.
22
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Copyright © 2013, Texas Instruments Incorporated



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