MSP430F5259 datasheet(24/107 Pages) TI1

24 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

Table 11. Port Mapping Mnemonics and Functions (continued)

VALUE

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

PM_UCA0RXD

USCI_A0 UART RXD (direction controlled by USCI - input)

PM_UCA0SOMI

USCI_A0 SPI slave out master in (direction controlled by USCI)

PM_UCA0TXD

USCI_A0 UART TXD (direction controlled by USCI - output)

PM_UCA0SIMO

USCI_A0 SPI slave in master out (direction controlled by USCI)

PM_UCA0CLK

USCI_A0 clock input/output (direction controlled by USCI)

PM_UCB0STE

USCI_B0 SPI slave transmit enable (direction controlled by USCI)

PM_UCB0SOMI

USCI_B0 SPI slave out master in (direction controlled by USCI)

PM_UCB0SCL

USCI_B0 I2C clock (open drain and direction controlled by USCI)

PM_UCB0SIMO

USCI_B0 SPI slave in master out (direction controlled by USCI)

PM_UCB0SDA

USCI_B0 I2C data (open drain and direction controlled by USCI)

PM_UCB0CLK

USCI_B0 clock input/output (direction controlled by USCI)

PM_UCA0STE

USCI_A0 SPI slave transmit enable (direction controlled by USCI)

PM_UCA3RXD

USCI_A3 UART RXD (direction controlled by USCI - input)

PM_UCA3SOMI

USCI_A3 SPI slave out master in (direction controlled by USCI)

PM_UCA3TXD

USCI_A3 UART TXD (direction controlled by USCI - output)

PM_UCA3SIMO

USCI_A3 SPI slave in master out (direction controlled by USCI)

PM_UCB3SIMO

USCI_B3 SPI slave in master out (direction controlled by USCI)

PM_UCB3SDA

USCI_B3I2C data (open drain and direction controlled by USCI)

PM_UCB3SOMI

USCI_B3 SPI slave out master in (direction controlled by USCI)

PM_UCB3SCL

USCI_B3 I2C clock (open drain and direction controlled by USCI)

Reserved

Disables the output driver and the input Schmitt trigger to prevent parasitic

31 (0FFh)(1)

PM_ANALOG

cross currents when applying analog signals

(1)

The value of the PM_ANALOG mnemonic is set to 0FFh. The port mapping registers are only 5 bits wide and the upper bits are ignored

resulting in a read out value of 31.

Table 12. Default Mapping

PxMAPy MNEMONIC

INPUT PIN FUNCTION

OUTPUT PIN FUNCTION

USCI_B1 SPI slave transmit enable (direction controlled by USCI)

P4.0/P4MAP0

PM_UCB1STE/PM_UCA1CLK

USCI_A1 clock input/output (direction controlled by USCI)

USCI_B1 SPI slave in master out (direction controlled by USCI)

P4.1/P4MAP1

PM_UCB1SIMO/PM_UCB1SDA

USCI_B1 I2C data (open drain and direction controlled by USCI)

USCI_B1 SPI slave out master in (direction controlled by USCI)

P4.2/P4MAP2

PM_UCB1SOMI/PM_UCB1SCL

USCI_B1 I2C clock (open drain and direction controlled by USCI)

USCI_A1 SPI slave transmit enable (direction controlled by USCI)

P4.3/P4MAP3

PM_UCB1CLK/PM_UCA1STE

USCI_B1 clock input/output (direction controlled by USCI)

USCI_A1 UART TXD (Direction controlled by USCI - output)

P4.4/P4MAP4

PM_UCA1TXD/PM_UCA1SIMO

USCI_A1 SPI slave in master out (direction controlled by USCI)

USCI_A1 UART RXD (Direction controlled by USCI - input)

P4.5/P4MAP5

PM_UCA1RXD/PM_UCA1SOMI

USCI_A1 SPI slave out master in (direction controlled by USCI)

USCI_A3 UART TXD (Direction controlled by USCI - output)

P4.6/P4MAP6

PM_UCA3TXD/PM_UCA3SIMO

USCI_A3 SPI slave in master out (direction controlled by USCI)

USCI_A3 UART RXD (Direction controlled by USCI - input)

P4.7/P4MAP7

PM_UCA3RXD/PM_UCA3SOMI

USCI_A3 SPI slave out master in (direction controlled by USCI)

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