MSP430F5259 datasheet(64/107 Pages) TI1

64 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

USCI (UART Mode), Recommended Operating Conditions

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK, ACLK

fUSCI

USCI input clock frequency

External: UCLK

fSYSTEM

MHz

Duty cycle = 50% ± 10%

BITCLK clock frequency

fBITCLK

MHz

(equals baud rate in MBaud)

USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

VCC

VIO

MIN

MAX

UNIT

1.8 V

1.62 V to 1.80 V

600

tτ

UART receive deglitch time(1)

3.0 V

1.62 V to 1.98 V

600

(1)

Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To make sure that pulses are

correctly recognized, their duration should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode), Recommended Operating Conditions

PARAMETER

CONDITIONS

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

fUSCI

USCI input clock frequency

fSYSTEM

MHz

Duty cycle = 50% ± 10%

USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(see Note

(1), Figure 14 and Figure 15)

PARAMETER

TEST CONDITIONS

VCC

VIO

MIN

MAX

UNIT

SMCLK or ACLK,

fUSCI

USCI input clock frequency

fSYSTEM

MHz

Duty cycle = 50% ± 10%

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tSU,MI

SOMI input data setup time

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tHD,MI

SOMI input data hold time

2.4 V

1.62 V to 1.98 V

PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

UCLK edge to SIMO valid,

CL = 20 pF, PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

tVALID,MO

SIMO output data valid time(2)

2.4 V

1.62 V to 1.98 V

UCLK edge to SIMO valid,

CL = 20 pF, PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

1.8 V

1.62 V to 1.80 V

-10

CL = 20 pF, PMMCOREV = 0

3.0 V

1.62 V to 1.98 V

-10

tHD,MO

SIMO output data hold time(3)

2.4 V

1.62 V to 1.98 V

-10

CL = 20 pF, PMMCOREV = 3

3.0 V

1.62 V to 1.98 V

-10

(1)

fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).

For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) see the SPI parameters of the attached slave.

(2)

Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams

in Figure 14 and Figure 15.

(3)

Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data

on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in

Figure 14 and Figure 15.

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MSP430F5259 Datasheet(PDF) 64 Page - Texas Instruments

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