MSP430F5259 datasheet(44/107 Pages) TI1

44 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

Voltage applied at VCC to VSS

–0.3 V to 4.1 V

Voltage applied at VIO to VSS

–0.3 V to 2.2 V

Voltage applied to any pin (excluding VCORE and VIO pins)

(2)

–0.3 V to VCC + 0.3 V

Voltage applied to VIO pins

–0.3 V to VIO + 0.2 V

Diode current at any device pin

±2 mA

Storage temperature range, Tstg

(3)

–55°C to 150°C

(1)

Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.

(3)

Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions

Typical values are specified at VCC = 3.3 V and TA = 25°C (unless otherwise noted)

MIN

NOM

MAX

UNIT

PMMCOREVx = 0

1.8

3.6

PMMCOREVx = 0, 1

2.0

3.6

Supply voltage during program execution and flash

VCC

programming (AVCC = DVCC)

(1) (2) (3)

PMMCOREVx = 0, 1, 2

2.2

3.6

PMMCOREVx = 0, 1, 2, 3

2.4

3.6

VIO

Supply voltage applied to DVIO referenced to VSS

(2)

1.62

1.98

VSS

Supply voltage (AVSS = DVSS)

Operating free-air temperature

–40

°C

Operating junction temperature

–40

°C

CVCORE

Recommended capacitor at VCORE

470

CDVCC/

Capacitor ratio of DVCC to VCORE

CVCORE

PMMCOREVx = 0 (default

condition),

8.0

1.8 V

≤ VCC ≤ 3.6 V

PMMCOREVx = 1,

12.0

Processor frequency (maximum MCLK frequency)(4)

2.0 V

≤ VCC ≤ 3.6 V

fSYSTEM

MHz

(see Figure 4)

PMMCOREVx = 2,

20.0

2.2 V

≤ VCC ≤ 3.6 V

PMMCOREVx = 3,

25.0

2.4 V

≤ VCC ≤ 3.6 V

(1)

It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be

tolerated during power up and operation.

(2)

During VCC and VIO power up, it is required that VIO ≥ VCC during the ramp up phase of VIO. During VCC and VIO power down, it is

required that VIO ≥ VCC during the ramp down phase of VIO (see Figure 2).

(3)

The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the PMM, SVS High Side threshold

parameters for the exact values and further details.

(4)

Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.

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