MSP430F5259 datasheet(68/107 Pages) TI1

68 / 107 page

SDA

SCL

HD,DAT

SU,DAT

HD,STA

HIGH

LOW

BUF

HD,STA

SU,STA

SU,STO

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18)

PARAMETER

TEST CONDITIONS

VCC

VIO

(1)

MIN

MAX

UNIT

Internal: SMCLK or ACLK,

fUSCI

USCI input clock frequency

External: UCLK,

fSYSTEM

MHz

Duty cycle = 50% ± 10%

fSCL

SCL clock frequency

2.2 V, 3 V

1.62 V to 1.98 V

400

kHz

fSCL ≤ 100 kHz

4.0

tHD,STA

Hold time (repeated) START

2.2 V, 3 V

1.62 V to 1.98 V

µs

fSCL > 100 kHz

0.6

fSCL ≤ 100 kHz

4.7

Setup time for a repeated

tSU,STA

2.2 V, 3 V

1.62 V to 1.98 V

µs

START

fSCL > 100 kHz

0.6

tHD,DAT

Data hold time

2.2 V, 3 V

1.62 V to 1.98 V

tSU,DAT

Data setup time

2.2 V, 3 V

1.62 V to 1.98 V

250

fSCL ≤ 100 kHz

4.0

tSU,STO

Setup time for STOP

2.2 V, 3 V

1.62 V to 1.98 V

µs

fSCL > 100 kHz

0.6

Pulse duration of spikes

tSP

2.2 V, 3 V

1.62 V to 1.98 V

600

suppressed by input filter

(1)

In all test conditions, VIO ≤ VCC

Figure 18. I2C Mode Timing

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