MSP430F5259 datasheet(11/107 Pages) TI1

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

www.ti.com

SLAS903A – MAY 2013 – REVISED JULY 2013

Table 3. Terminal Functions (continued)

TERMINAL

NO.

I/O(1)

DESCRIPTION

NAME

RGC

ZQE

YFF

General-purpose digital I/O

B8,

P7.0/UCA2TXD/UCA2SIMO (7)

I/O

Transmit data – USCI_A2 UART mode

Slave in, master out – USCI_A2 SPI mode

General-purpose digital I/O

P7.1/UCA2RXD/UCA2SOMI(7)

I/O

Receive data – USCI_A2 UART mode

Slave out, master in – USCI_A2 SPI mode

General-purpose digital I/O

Clock signal input – USCI_B2 SPI slave mode

P7.2/UCB2CLK/UCA2STE(7)

I/O

Clock signal output – USCI_B2 SPI master mode

Slave transmit enable – USCI_A2 SPI mode

General-purpose digital I/O

P7.3/UCB2SIMO/UCB2SDA (7)

I/O

Slave in, master out – USCI_B2 SPI mode

I2C data – USCI_B2 I2C mode

General-purpose digital I/O

P7.4/UCB2SOMI/UCB2SCL(7)

I/O

Slave out, master in – USCI_B2 SPI mode

I2C clock – USCI_B2 I2C mode

General-purpose digital I/O

Slave transmit enable – USCI_B2 SPI mode

P7.5/UCB2STE/UCA2CLK(8)

I/O

Clock signal input – USCI_A2 SPI slave mode

Clock signal output – USCI_A2 SPI master mode

BSLEN(8)

BSL enable with internal pulldown

Reset input active low(9)(10)

RST/NMI(8)

Non-maskable interrupt input(9)

General-purpose digital I/O

P5.2/XT2IN

I/O

Input terminal for crystal oscillator XT2(11)

General-purpose digital I/O

P5.3/XT2OUT

I/O

Output terminal of crystal oscillator XT2

Test mode pin – Selects four wire JTAG operation

TEST/SBWTCK(12)

Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated

General-purpose digital I/O

PJ.0/TDO(13)

I/O

JTAG test data output port

General-purpose digital I/O

PJ.1/TDI/TCLK(13)

I/O

JTAG test data input or test clock input

General-purpose digital I/O

PJ.2/TMS(13)

I/O

JTAG test mode select

General-purpose digital I/O

PJ.3/TCK(13)

I/O

JTAG test clock

(8)

This pin function is supplied by DVIO. See Electrical Characteristics for input and output requirements.

(9)

This pin is configurable as reset or NMI and resides on the DVIO supply domain. When driven from external, the input swing levels from

DVSS to DVIO are required.

(10) When this pin is configured as reset, the internal pullup resistor is enabled by default.

(11) When in crystal bypass mode, XT2IN can be configured so that it can support an input digital waveform with swing levels from DVSS to

DVCC or DVSS to DVIO. In this case, it is required that the pin be configured properly for the intended input swing.

(12) See Bootstrap Loader - I2C andJTAG Operation for use with BSL and JTAG functions.

(13) See JTAG Operation for use with JTAG function.

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