MSP430F5259 datasheet(32/107 Pages) TI1

32 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

SLAS903A – MAY 2013 – REVISED JULY 2013

www.ti.com

Peripheral File Map

Table 19. Peripherals

OFFSET ADDRESS

MODULE NAME

BASE ADDRESS

RANGE

Special Functions (see Table 20)

0100h

000h-01Fh

PMM (see Table 21)

0120h

000h-010h

Flash Control (see Table 22)

0140h

000h-00Fh

CRC16 (see Table 23)

0150h

000h-007h

RAM Control (see Table 24)

0158h

000h-001h

Watchdog (see Table 25)

015Ch

000h-001h

UCS (see Table 26)

0160h

000h-01Fh

SYS (see Table 27)

0180h

000h-01Fh

Shared Reference (see Table 28)

01B0h

000h-001h

Port Mapping Control (see Table 29)

01C0h

000h-002h

Port Mapping Port P4 (see Table 29)

01E0h

000h-007h

Port P1, P2 (see Table 30)

0200h

000h-01Fh

Port P3, P4 (see Table 31)

0220h

000h-00Bh

Port P5, P6 (see Table 32)

0240h

000h-01Fh

Port P7 (see Table 33)

0260h

000h-00Bh

Port PJ (see Table 34)

0320h

000h-01Fh

TA0 (see Table 35)

0340h

000h-02Eh

TA1 (see Table 36)

0380h

000h-02Eh

TB0 (see Table 37)

03C0h

000h-02Eh

TA2 (see Table 38)

0400h

000h-02Eh

Real-Time Clock (RTC_A) (see Table 39)

04A0h

000h-01Bh

32-Bit Hardware Multiplier (see Table 40)

04C0h

000h-02Fh

DMA General Control (see Table 41)

0500h

000h-00Fh

DMA Channel 0 (see Table 41)

0510h

000h-00Ah

DMA Channel 1 (see Table 41)

0520h

000h-00Ah

DMA Channel 2 (see Table 41)

0530h

000h-00Ah

USCI_A0 (see Table 42)

05C0h

000h-01Fh

USCI_B0 (see Table 43)

05E0h

000h-01Fh

USCI_A1 (see Table 44)

0600h

000h-01Fh

USCI_B1 (see Table 45)

0620h

000h-01Fh

USCI_A2 (see Table 42)

0640h

000h-01Fh

USCI_B2 (see Table 43)

0660h

000h-01Fh

USCI_A3 (see Table 44)

0680h

000h-01Fh

USCI_B3 (see Table 45)

06A0h

000h-01Fh

ADC10_A (see Table 50)

0740h

000h-01Fh

Comparator_B (see Table 51)

08C0h

000h-00Fh

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