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MSP430F5259 Datasheet(PDF) 30 Page - Texas Instruments

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Part # MSP430F5259
Description  MSP430F525x Mixed Signal Microcontroller
PDF  107 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430F5259 Datasheet(HTML) 30 Page - Texas Instruments

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MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256
MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252
SLAS903A – MAY 2013 – REVISED JULY 2013
www.ti.com
TB0 (Link to user's guide)
TB0 is a 16-bit timer/counter (Timer_B type) with seven capture/compare registers. It can support multiple
captures or compares, PWM outputs, and interval timing. It also has extensive interrupt capabilities. Interrupts
may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table 18. TB0 Signal Connections
INPUT PIN NUMBER
OUTPUT PIN NUMBER
DEVICE INPUT
MODULE INPUT
MODULE
DEVICE OUTPUT
MODULE BLOCK
SIGNAL
SIGNAL
OUTPUT SIGNAL
SIGNAL
RGC, ZQE, YFF
RGC, ZQE, YFF
(1)
TB0CLK
TBCLK
ACLK (internal)
ACLK
Timer
NA
NA
SMCLK (internal)
SMCLK
(1)
TB0CLK
TBCLK
(1)
TB0.0
CCI0A
(1)
ADC10 (internal)
(1)
TB0.0
CCI0B
ADC10SHSx = {2}
CCR0
TB0
TB0.0
DVSS
GND
DVCC
VCC
(1)
TB0.1
CCI1A
(1)
ADC10 (internal)
CBOUT (internal)
CCI1B
ADC10SHSx = {3}
CCR1
TB1
TB0.1
DVSS
GND
DVCC
VCC
(1)
TB0.2
CCI2A
(1)
(1)
TB0.2
CCI2B
CCR2
TB2
TB0.2
DVSS
GND
DVCC
VCC
(1)
TB0.3
CCI3A
(1)
(1)
TB0.3
CCI3B
CCR3
TB3
TB0.3
DVSS
GND
DVCC
VCC
(1)
TB0.4
CCI4A
(1)
(1)
TB0.4
CCI4B
CCR4
TB4
TB0.4
DVSS
GND
DVCC
VCC
(1)
TB0.5
CCI5A
(1)
(1)
TB0.5
CCI5B
CCR5
TB5
TB0.5
DVSS
GND
DVCC
VCC
(1)
TB0.6
CCI6A
(1)
ACLK (internal)
CCI6B
CCR6
TB6
TB0.6
DVSS
GND
DVCC
VCC
(1)
Timer functions can be selected by the port mapping controller.
Comparator_B (Link to user's guide)
The primary function of the Comparator_B module is to support precision slope analog-to-digital conversions,
battery voltage supervision, and monitoring of external analog signals.
ADC10_A (Link to user's guide)
The ADC10_A module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR
core, sample select control, reference generator, and a conversion result buffer. A window comparator with lower
and upper limits allows CPU-independent result monitoring with three window comparator interrupt flags.
30
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