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MSP430F5259 Datasheet(PDF) 23 Page - Texas Instruments |
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MSP430F5259 Datasheet(HTML) 23 Page - Texas Instruments |
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23 / 107 page  MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 www.ti.com SLAS903A – MAY 2013 – REVISED JULY 2013 Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x5xx and MSP430x6xx Family User's Guide (SLAU208). Digital I/O (Link to user's guide) • All individual I/O bits are independently programmable. • Any combination of input, output, and interrupt conditions is possible. • Pullup or pulldown on all ports is programmable. • Drive strength on all ports is programmable. • Edge-selectable interrupt and LPM4.5 wakeup input capability is available for all bits of ports P1, P2. • Edge-selectable interrupt capability is available for all bits of port P6. • Read and write access to port-control registers is supported by all instructions. • Ports can be accessed byte-wise or word-wise in pairs. Port Mapping Controller (Link to user's guide) The port mapping controller allows the flexible and reconfigurable mapping of digital functions to port P4. Table 11. Port Mapping Mnemonics and Functions VALUE PxMAPy MNEMONIC INPUT PIN FUNCTION OUTPUT PIN FUNCTION 0 PM_NONE None DVSS PM_CBOUT0 - COMP_B output 1 PM_TB0CLK TB0 clock input PM_ADC10CLK - ADC10CLK 2 PM_DMAE0 DMAE0 input PM_SVMOUT - SVM output 3 PM_TB0OUTH TB0 high-impedance input TB0OUTH 4 PM_TB0CCR0A TB0 CCR0 capture input CCI0A TB0 CCR0 compare output Out0 5 PM_TB0CCR1A TB0 CCR1 capture input CCI1A TB0 CCR1 compare output Out1 6 PM_TB0CCR2A TB0 CCR2 capture input CCI2A TB0 CCR2 compare output Out2 7 PM_TB0CCR3A TB0 CCR3 capture input CCI3A TB0 CCR3 compare output Out3 8 PM_TB0CCR4A TB0 CCR4 capture input CCI4A TB0 CCR4 compare output Out4 9 PM_TB0CCR5A TB0 CCR5 capture input CCI5A TB0 CCR5 compare output Out5 10 PM_TB0CCR6A TB0 CCR6 capture input CCI6A TB0 CCR6 compare output Out6 PM_UCA1RXD USCI_A1 UART RXD (direction controlled by USCI - input) 11 PM_UCA1SOMI USCI_A1 SPI slave out master in (direction controlled by USCI) PM_UCA1TXD USCI_A1 UART TXD (direction controlled by USCI - output) 12 PM_UCA1SIMO USCI_A1 SPI slave in master out (direction controlled by USCI) PM_UCA1CLK USCI_A1 clock input/output (direction controlled by USCI) 13 PM_UCB1STE USCI_B1 SPI slave transmit enable (direction controlled by USCI) PM_UCB1SOMI USCI_B1 SPI slave out master in (direction controlled by USCI) 14 PM_UCB1SCL USCI_B1 I2C clock (open drain and direction controlled by USCI) PM_UCB1SIMO USCI_B1 SPI slave in master out (direction controlled by USCI) 15 PM_UCB1SDA USCI_B1 I2C data (open drain and direction controlled by USCI) PM_UCB1CLK USCI_B1 clock input/output (direction controlled by USCI) 16 PM_UCA1STE USCI_A1 SPI slave transmit enable (direction controlled by USCI) 17 PM_CBOUT1 None COMP_B output 18 PM_MCLK None MCLK 19 PM_RTCCLK None RTCCLK output Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 23 |
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