MSP430F5259 datasheet(69/107 Pages) TI1

69 / 107 page

MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256

MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252

www.ti.com

SLAS903A – MAY 2013 – REVISED JULY 2013

10-Bit ADC, Power Supply and Input Range Conditions

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

(1)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

AVCC and DVCC are connected together,

AVCC

Analog supply voltage

AVSS and DVSS are connected together,

1.8

3.6

V(AVSS) = V(DVSS) = 0 V

All ADC10_A pins: P1.0 to P1.5 and P3.6 and

V(Ax)

Analog input voltage range(2)

AVCC

P3.7 terminals

fADC10CLK = 5.0 MHz, ADC10ON = 1,

2.2 V

100

Operating supply current into

AVCC terminal, REF module

REFON = 0, SHT0 = 0, SHT1 = 0,

µA

3 V

110

and reference buffer off

ADC10DIV = 0, ADC10SREF = 00

fADC10CLK = 5.0 MHz, ADC10ON = 1,

Operating supply current into

AVCC terminal, REF module

REFON = 1, SHT0 = 0, SHT1 = 0,

3 V

113

150

µA

on, reference buffer on

ADC10DIV = 0, ADC10SREF = 01

fADC10CLK = 5.0 MHz, ADC10ON = 1,

IADC10_A

Operating supply current into

REFON = 0, SHT0 = 0, SHT1 = 0,

AVCC terminal, REF module

3 V

105

140

µA

ADC10DIV = 0, ADC10SREF = 10,

off, reference buffer on

VEREF = 2.5 V

fADC10CLK = 5.0 MHz, ADC10ON = 1,

Operating supply current into

REFON = 0, SHT0 = 0, SHT1 = 0,

AVCC terminal, REF module

3 V

110

µA

ADC10DIV = 0, ADC10SREF = 11,

off, reference buffer off

VEREF = 2.5 V

Only one terminal Ax can be selected at one

Input capacitance

time from the pad to the ADC10_A capacitor

2.2 V

3.5

array including wiring and pad

AVCC > 2 V, 0 V ≤ VAx ≤ AVCC

Input MUX ON resistance

Ω

1.8 V < AVCC < 2 V, 0 V ≤ VAx ≤ AVCC

(1)

The leakage current is defined in the leakage current table with P6.x/Ax parameter.

(2)

The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results. The external

reference voltage requires decoupling capacitors. See ().

10-Bit ADC, Timing Parameters

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

For specified performance of ADC10_A linearity

fADC10CLK

2.2 V, 3 V

0.45

5.5

MHz

parameters

Internal ADC10_A

fADC10OSC

ADC10DIV = 0, fADC10CLK = fADC10OSC

2.2 V, 3 V

4.2

4.8

5.4

MHz

oscillator(1)

REFON = 0, Internal oscillator, 12 ADC10CLK

cycles, 10-bit mode

2.2 V, 3 V

2.4

3.0

fADC10OSC = 4 MHz to 5 MHz

tCONVERT

Conversion time

µs

External fADC10CLK from ACLK, MCLK or SMCLK,

ADC10SSEL

≠ 0

Turn on settling time of

(2)t

ADC10ON

See (3)

100

the ADC

1.8 V

µs

tSample

Sampling time

RS = 1000 Ω, RI = 96 k Ω, CI = 3.5 pF

(4)

3.0 V

µs

(1)

The ADC10OSC is sourced directly from MODOSC inside the UCS.

(2)

12 × ADC10DIV × 1/fADC10CLK

(3)

The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already

settled.

(4)

Approximately eight Tau (

τ) are needed to get an error of less than ±0.5 LSB

Submit Documentation Feedback

MSP430F5259 Datasheet(PDF) 69 Page - Texas Instruments

MSP430F5259 Datasheet(HTML) 69 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL