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MSP430F5259 Datasheet(PDF) 74 Page - Texas Instruments |
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MSP430F5259 Datasheet(HTML) 74 Page - Texas Instruments |
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74 / 107 page  BSLEN RST/NMI (DVIO domain) t V IT- V IT+ V IT+ t SU,BSLEN V IT- t HO,BSLEN MSP430F5259, MSP430F5258, MSP430F5257, MSP430F5256 MSP430F5255, MSP430F5254, MSP430F5253, MSP430F5252 SLAS903A – MAY 2013 – REVISED JULY 2013 www.ti.com DVIO BSL Entry over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC VIO MIN MAX UNIT tSU, BSLEN Setup time, BSLEN to RST/NMI(1) 2.2 V, 3 V 1.62 V to 1.98 V 100 ns tHO, BSLEN Hold time, BSLEN to RST/NMI(2) 2.2 V, 3 V 1.62 V to 1.98 V 350 µs (1) AVCC, DVCC, DVIO stable and within specification. (2) BSLEN must remain logically high long enough for the boot code to detect its level and enter the BSL sequence. After the minimum hold time is achieved, BSLEN is a don't care. Figure 19. DVIO BSL Entry Timing 74 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated |
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