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PCI9060ES Datasheet(PDF) 22 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 22 Page - List of Unclassifed Manufacturers |
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22 / 192 page ![]() SECTION 3 PCI 9080 FUNCTIONAL DESCRIPTION ©PLX Technology, Inc., 1997 Page 13 Version 1.02 Table 3-1. NB# and Serial EEPROM Guidelines NB# Serial EEPROM System Boot Condition No Boot with PCI 9080 default values. Programmed Boot with serial EEPROM values. Low Blank Not recommended (uses default values). No Local processor programs PCI 9080 registers, then sets Local Init Status (Table 4-59[31] = done). Note: Some systems hang if Direct Slave reads and writes take too long (during initialization, the PCI host also performs Direct Slave accesses). Value of PCI Target Retry Delay Clocks (Table 4-39[31:28]) may resolve this problem. Programmed Load serial EEPROM, but local processor can reprogram PCI 9080. High Blank Load serial EEPROM (default values), but local processor can reprogram PCI 9080. System can boot. Note: Serial EEPROM can be programmed through PCI 9080 after system boots in this condition. 3.2.1 Serial EEPROM Initialization During serial EEPROM initialization, PCI 9080 response to PCI target accesses is RETRY. During serial EEPROM initialization, PCI 9080 response to a local processor is to hold off READYo#. 3.2.2 Local Initialization PCI 9080 issues a RETRY to all PCI accesses until the "Local Init Done bit" in the Init Control Register is set. "Init Done bit" is programmable through local bus configuration accesses. If this bit is not going to be set by a local processor, then NB# input should be tied low. Holding NB# input low externally forces the Local Init Done bit to 1. PCI 9080 default values are used if a serial EEPROM is not present and local Init Status bit is set to 1 by holding the NB# input low or set by the local processor. 3.3 SERIAL EEPROM After reset, PCI 9080 attempts to read the serial EEPROM to determine its presence. An active low start bit indicates the serial EEPROM is present (PCI 9080 supports 93CS46 (1K) or 93CS56 (2K), selectable by way of the EESEL pin). (Refer to the manufacturer’s data sheet for the particular serial EEPROM being used.) The first word is then checked to verify the serial EEPROM is programmed. If the first word (16 bit) is all ones, a blank serial EEPROM PCI 9080 uses default values instead. The 5 V serial EEPROM clock (EESK, pin 173) is derived from the PCI clock. PCI 9080 generates the serial EEPROM clock by internally dividing the PCI clock by 32. The serial EEPROM can be read or programmed from the PCI or local bus. Bits [27:24] of the Serial EEPROM Control Register (refer to Table 4-59[27:24]) controls the PCI 9080 pins that enable the reading or writing of serial EEPROM data bits. (Refer to the manufacturer’s data sheet for the particular serial EEPROM being used.) PCI 9080 has three serial EEPROM load options: • Short Load Mode—SHORT# input pin is pulled down and PCI 9080 loads five Lwords from the serial EEPROM • Long Load Mode—SHORT# input pin is pulled up, bit 25 of the Local Bus Region Descriptor Register (LOC:98h) is set to 0, and PCI 9080 loads 17 Lwords from the serial EEPROM (refer to Table 4-39) • Extra Long Load Mode—SHORT# input pin is pulled up, bit 25 of the Local Bus Region Descriptor Register (LOC:98h) is set to 1 during Long Load from the serial EEPROM, and PCI 9080 loads 21 Lwords from the serial EEPROM (refer to Table 4-39) 3.3.1 Short Serial EEPROM Load The registers listed in Table 3-2 are loaded from serial EEPROM after reset is de-asserted if SHORT# pin is low. The serial EEPROM is organized in words (16 bit). PCI 9080 first loads MSW (Most Significant Word; bits [31:16]), starting from the most significant bit (bit 31). PCI 9080 then loads LSW (Least Significant Word; bits [15:0]), starting again from the most significant bit (bit 15). Therefore, PCI 9080 loads Device ID, Vendor ID, class code, and so forth. The five 32-bit words are stored sequentially in the serial EEPROM. |
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