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PCI9060ES Datasheet(PDF) 94 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 94 Page - List of Unclassifed Manufacturers |
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94 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 85 Version 1.02 4.7.4 (OQP; PCI:44h) Outbound Queue Port Register Table 4-78. (OQP; PCI:44h) Outbound Queue Port Register Field Description Read Write Value after Reset 31:0 Value written by PCI master is stored into the Outbound Free List FIFO, which is located in local memory at the address pointed to by the Queue Base Address + (3*FIFO Size) + Outbound Free Head Pointer. From the time of the PCI write until the local memory write and update of the Outbound Free Head Pointer, further accesses to this register result in a retry. If FIFO fills up, a local LSERR interrupt is generated. When the port is read by the PCI master, the value is read from the Outbound Post List FIFO, which is located in local memory at the address pointed to by the Queue Base Address + (2*FIFO Size) + Outbound Post Tail Pointer. If FIFO is empty, a value of FFFFFFFh is returned. A PCI interrupt is generated if Outbound Post List FIFO is not empty. PCI PCI 0 4.7.5 (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register Table 4-79. (MQCR; PCI:C0h, LOC:140h) Messaging Queue Configuration Register Field Description Read Write Value after Reset 0 Queue Enable. Value of 1 allows accesses to the Inbound and Outbound Queue ports. If cleared to 0, writes are accepted but ignored and reads return FFFFFFFF. All pointer initialization and frame allocation should be completed before enabling this bit. Yes Yes 0 5:1 Circular FIFO Size. Defines the size of one of the circular FIFOs. Each of the four FIFOs are the same size. Each FIFO entry is one 32 bit word. FIFO Size Encoding Max entries FIFO Total FIFO 5:1 per FIFO Size Memory 00001 4K entries 16 KB 64 KB 00010 8K entries 32 KB 128 KB 00100 16K entries 64 KB 256 KB 01000 32K entries 128 KB 512 KB 10000 64K entries 256 KB 1 MB Yes Yes 00001 31:6 Reserved. Yes No 0 4.7.6 (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register Table 4-80. (QBAR; PCI:C4h, LOC:144h) Queue Base Address Register Field Description Read Write Value after Reset 19:0 Reserved. Yes No 0 31:20 Queue Base Address. Local memory base address of the Inbound and Outbound Queues (four contiguous and equal size FIFOs). Queue base address must be aligned on a 1 MB boundary. Yes Yes 0 |
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