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PCI9060ES Datasheet(PDF) 59 Page - List of Unclassifed Manufacturers

Part # PCI9060ES
Description  12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS
PDF  192 Pages
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Manufacturer  ETC [List of Unclassifed Manufacturers]
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PCI9060ES Datasheet(HTML) 59 Page - List of Unclassifed Manufacturers

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SECTION 4
PCI 9080
REGISTERS
©PLX Technology, Inc., 1997
Page 50
Version 1.02
4.2 REGISTER ADDRESS MAPPING
4.2.1 PCI Configuration Registers
Table 4-5. PCI Configuration Registers
To ensure software compatibility with other versions of the PCI 9080 family and to
ensure compatibility with future enhancements,
write a zero to all unused bits.
PCI CFG
Register
Address
Local
Access
(Offset
from Chip
Select
Address)
31
24
23
16
15
8
70
PCI/Local
Writable
Serial
EEPROM
Writable
00h
00h
Device ID
Vendor ID
Local
Y
04h
04h
Status
Command
Y
N
08h
08h
Class Code
Revision ID
Local
Y
0Ch
0Ch
BIST
Header Type
PCI Latency Timer
Cache Line Size
Y [15:0],
Local
N
10h
10h
PCI Base Address 0 for Memory Mapped Configuration Registers (PCIBAR0)
Y
N
14h
14h
PCI Base Address 1 for I/O Mapped Configuration Registers (PCIBAR1)
Y
N
18h
18h
PCI Base Address 2 for Local Address Space 0 (PCIBAR2)
Y
N
1Ch
1Ch
PCI Base Address 3 for Local Address Space 1 (PCIBAR3)
Y
N
20h
20h
Unused Base Address (PCIBAR4)
N
N
24h
24h
Unused Base Address (PCIBAR5)
N
N
28h
28h
Cardbus CIS Pointer (Not Supported)
N
N
2Ch
2Ch
Subsystem ID
Subsystem Vendor ID
Local
Y
30h
30h
PCI Base Address for Local Expansion ROM
Y
N
34h
34h
Reserved
N
N
38h
38h
Reserved
N
N
3Ch
3Ch
Max_Lat
Min_Gnt
Interrupt Pin
Interrupt Line
Y [7:0],
Local
Y
Note:
Refer to the PCI 2.1 spec for definitions of these registers.



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