PCI9060ES datasheet(15/192 Pages) ETC

15 / 192 page

SECTION 2

PCI 9080

BUS OPERATION

©PLX Technology, Inc., 1997

Page 6

Version 1.02

2. BUS OPERATION

2.1 PCI BUS CYCLES

PCI 9080 is compliant with PCI Specification v2.1. Refer

to the PCI 2.1 spec for any specific features of the PCI

bus.

2.1.1 PCI Target Command Codes

As a target, PCI 9080 allows access to PCI 9080 internal

registers and local bus, using the commands listed in

Table 2-1.

Table 2-1. PCI Target Command Codes

Command Type

Code (C/BE[3:0]#)

I/O Read

0010 (2h)

I/O Write

0011 (3h)

Memory Read

0110 (6h)

Memory Write

0111 (7h)

Memory Read Multiple

1100 (Ch)

Memory Read Line

1110 (Eh)

Memory Write and Invalidate

1111 (Fh)

Configuration Read

1010 (Ah)

Configuration Write

1011 (Bh)

All read or write accesses to PCI 9080 can be byte,

word, or longword (Lword) accesses. All memory

commands are aliased to the basic memory commands.

All I/O accesses to PCI 9080 are decoded to an Lword

boundary. The byte enables are used to determine

which bytes are read or written. An I/O access with

illegal byte enable combinations is terminated with a

Target Abort.

2.1.2 PCI Master Command Codes

PCI 9080 can access the PCI bus to perform DMA

transfers or Direct Master Local to PCI Bus transfers.

During the Direct master or DMA transfer, the command

code assigned to PCI 9080 internal register location

(PCI:6Ch)(LOC:ECh) bits [15:0] is used as the PCI

command code (refer to Table 4-59[15:0]). Table 2-2

through Table 2-5 list the various PCI Master Command

codes.

Note:

Programmable internal registers determine PCI

command codes when the PCI 9080 is master.

Note:

DMA

cannot

perform

I/O

configuration

accesses.

2.1.2.1 DMA Master Command Codes

DMA controllers of PCI 9080 can generate the memory

cycles listed in Table 2-2.

Table 2-2. DMA Master Command Codes

Command Type

Code (C/BE[3:0]#)

Memory Read

0110 (6h)

Memory Write

0111 (7h)

Memory Read Multiple

1100 (Ch)

Memory Read Line

1110 (Eh)

Memory Write and Invalidate

1111 (Fh)

2.1.2.2 Direct

Local

PCI

Command

Codes

For direct local to PCI bus accesses, PCI 9080

generates the cycles listed in Table 2-3 through

Table 2-5.

Table 2-3. Local to PCI Memory Access

Command Type

Code (C/BE[3:0]#)

Memory Read

0110 (6h)

Memory Write

0111 (7h)

Memory Read Multiple

1100 (Ch)

Memory Read Line

1110 (Eh)

Table 2-4. Local to PCI I/O Access

Command Type

Code (C/BE[3:0]#)

I/O Read

0010 (2h)

I/O Write

0011 (3h)

Table 2-5. Local to PCI Configuration Access

Command Type

Code (C/BE[3:0]#)

Configuration Memory Read

1010 (Ah)

Configuration Memory Write

1011 (Bh)

2.1.3 PCI Arbitration

PCI 9080 asserts output REQ# to request the PCI bus.

PCI 9080 can be programmed using bit 23 of (PCI:08h

or PCI:ACh)(LOC:88h or LOC:12Ch) (refer to Table 4-

35[23]) to de-assert REQ# when it asserts FRAME#

during a bus master cycle, or to keep REQ# asserted for

the entire bus master cycle. PCI 9080 always de-asserts

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