PCI9060ES datasheet(45/192 Pages) ETC

45 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 36

Version 1.02

master abort and target abort interrupt bits in the PCI

Status configuration register.

Bits [26:24] of the Interrupt Control/Status Register (refer

to Table 4-58) are latched at the time of a target abort

interrupt

master

abort

interrupt.

They

provide

information as to who was master when an abort

occurred. PCI 9080 updates these bits whenever an

abort occurs.

3.12.2 Local Interrupts (LINTo#)

A PCI 9080 Local Interrupt (LINTo#) can be generated

by one of the following:

•

PCI to Local Doorbell/Mailboxes Register access

•

PCI BIST interrupt, the DMA done interrupt

•

DMA terminal count is reached

•

DMA abort interrupt or messaging outbound post

queue not empty

LINTo#, or individual sources of an interrupt, can be

enabled or disabled with the PCI 9080 Interrupt

Control/Status Register (refer to Table 4-58). Interrupt

Control/Status Register also provides interrupt status for

each source of the interrupt.

PCI 9080 local interrupt is a level output. An interrupt

can be cleared by disabling the interrupt enable bit of a

source or by clearing the cause of an interrupt.

3.12.2.1 Local to PCI Doorbell Interrupt

A local bus master can generate a PCI bus interrupt by

writing to the Local to PCI Doorbell Register (refer to

Table 4-57). PCI host processor can then read PCI 9080

Interrupt Control/Status Register (refer to Table 4-58) to

determine that a doorbell interrupt is pending. It can then

read the PCI 9080 Local to PCI Doorbell Register.

Each bit in the Local to PCI Doorbell Register is

individually controlled. Bits in the Doorbell Register can

only be set by the local side. From the local side, writing

a 1 to any bit position sets that bit and writing a 0 to a bit

position has no effect. Bits in the Local to PCI Doorbell

the PCI side, writing a 1 to any bit position clears that bit

and writing a 0 to a bit position has no effect.

The interrupt remains asserted as long as any of the

Local to PCI Doorbell Register bits are set and PCI

Doorbell interrupt is enabled.

To prevent race conditions when the PCI bus is

accessing the Doorbell Register (or any configuration

to prevent local bus accesses.

3.12.2.2 PCI to Local Doorbell Interrupt

A PCI bus master can generate a local bus interrupt by

writing to the PCI to Local Doorbell Register (refer to

Table 4-56). Local processor can then read the PCI

9080 Interrupt Control/Status Register (refer to Table 4-

58) to determine that a doorbell interrupt is pending. It

can then read the PCI 9080 PCI to Local Doorbell

Each bit in the PCI to Local Doorbell Register is

individually controlled. Bits in the Doorbell Register can

only be set by the PCI side. From the PCI side, writing 1

to any bit position sets that bit and writing 0 to a bit

position has no effect. Bits in the PCI to Local Doorbell

the local side, writing 1 to any bit position clears that bit

and writing 0 to a bit position has no effect.

Note:

If local side cannot clear Doorbell Interrupt, do

not use the PCI to Local Doorbell Register.

The interrupt remains asserted as long any of the PCI to

Local Doorbell Register bits are set and the Local

Doorbell interrupt is enabled.

To prevent race conditions when the local bus is

accessing the Doorbell Register (or any configuration

PCI bus.

3.12.2.3 Built-In Self Test Interrupt (BIST)

A PCI bus master can generate a local bus interrupt by

performing a PCI Type 0 configuration write to a bit in

the PCI BIST Register. The local processor can then

read the PCI 9080 Interrupt Control/Status Register

(refer to Table 4-58) to determine that a BIST interrupt is

pending.

The interrupt remains asserted as long as the bit is set

and the BIST interrupt is enabled. The local bus then

resets the bit when BIST is complete. PCI Host software

may fail the device if the bit is not reset after two

seconds.

Note:

PCI 9080 does not have internal BIST.

3.12.2.4 DMA Channel 0/1 Interrupts

A DMA channel can generate a PCI or local bus interrupt

when done (transfer complete) or after a transfer is

complete for a descriptor in chaining mode. A bit in the

DMA mode register determines whether to generate a

PCI or local interrupt. The local or PCI processor can

then read the PCI 9080 Interrupt Control/Status Register

(refer to Table 4-58) to determine whether a DMA

channel interrupt is pending.

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