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PCI9060ES Datasheet(PDF) 91 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 91 Page - List of Unclassifed Manufacturers |
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91 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 82 Version 1.02 4.6.11 (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register Table 4-72. (DMACSR0; PCI:A8h, LOC:128h) DMA Channel 0 Command/Status Register Field Description Read Write Value after Reset 0 Channel 0 Enable. Value of 1 enables channel to transfer data. Value of 0 disables channel from starting a DMA transfer and if in the process of transferring data suspend transfer (pause). Yes Yes 0 1 Channel 0 Start. Writing 1 to this bit causes channel to start transferring data if the channel is enabled. No Yes/Set 0 2 Channel 0 Abort. Writing 1 to this bit causes channel to abort the current transfer. Channel enable bit must be cleared. Channel complete bit is set when the abort is complete. No Yes/Set 0 3 Clear Interrupt. Writing 1 to this bit clears Channel 0 interrupts. No Yes/Clr 0 4 Channel 0 Done. Value of 1 indicates channel’s transfer is complete. Value of 0 indicates channel’s transfer is not complete. Yes No 1 7:5 Reserved. Yes No 0 4.6.12 (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register Table 4-73. (DMACSR1; PCI:A9h, LOC:129h) DMA Channel 1 Command/Status Register Field Description Read Write Value after Reset 0 Channel 1 Enable. Value of 1 enables channel to transfer data. Value of 0 disables channel from starting a DMA transfer and if in the process of transferring data suspend transfer (Pause). Yes Yes 0 1 Channel 1 Start. Writing 1 to this bit causes channel to start transferring data if channel is enabled. No Yes/Set 0 2 Channel 1 Abort. Writing 1 to this bit causes channel to abort the current transfer. Channel enable bit must be cleared. Channel complete bit is set when the abort is complete. No Yes/Set 0 3 Clear Interrupt. Writing 1 to this bit clears Channel 1 interrupts. No Yes/Clr 0 4 Channel 1 Done. Value of 1 indicates this channel’s transfer is complete. Value of 0 indicates channel’s transfer is not complete. Yes No 1 7:5 Reserved. Yes No 0 4.6.13 (DMAARB; PCI:ACh, LOC:12Ch) DMA Arbitration Register Same as Mode/Arbitration Register (MARBR) at address (PCI:08h)(LOC:88h) (refer to Table 4-35). |
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