PCI9060ES datasheet(51/192 Pages) ETC

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SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 42

Version 1.02

in the Outbound Free List FIFO. If Outbound Free List

FIFO is not empty (head and tail pointers are not equal),

the IOP can obtain the MFA of the oldest free outbound

message frame by reading the location pointed to by the

Queue Base Register + (3 * FIFO Size) + Outbound

Free Tail Pointer Register. After the IOP reads the MFA,

it must increment the Outbound Free Tail Pointer

that the number of message frames allocated should be

less than or equal to the number of entries in a FIFO.

MU also checks for overflows of the Outbound Free List

FIFO. When the head pointer is incremented and

becomes equal to the tail pointer, the Outbound Free

List FIFO is full, and the MU generates a local LSERR

(NMI) interrupt. The interrupt is recorded in the Queue

Status Control (QSR) Register.

From the time that the PCI write transaction is received

until the data is written into local memory and the

Outbound Free Head Pointer Register is incremented,

any PCI direct slave access to the PCI 9080 is issued a

RETRY.

Table 3-8. Circular FIFO Summary

FIFO

Name

PCI

Port

Generate PCI

Interrupt?

Generate Local

Interrupt

Head Pointer

Maintained by

Tail Pointer

Maintained by

Inbound Free

List FIFO

Inbound Queue

Port (Host read)

Local

processor

MU hardware

Inbound Post

List FIFO

Inbound Queue

Port (Host write)

Yes, when Port

is written

MU hardware

Local

processor

Outbound Post

List FIFO

Outbound Queue

Port (Host read)

Yes, when FIFO

is not empty

Local

processor

MU hardware

Outbound Free

List FIFO

Outbound Queue

Port (Host write)

Yes, (LSERR) when

FIFO full

MU hardware

Local

processor

3.13.10 I20 Enable Sequence

To enable I2O, the local processor should perform the

following:

•

Initialize Space 1 address and range

•

Initialize all FIFOs and message frame memory

•

Set the PCI class code in Register (PCI:09h-0Bh) to

be an I2O device with programming interface 01h

•

Set the I2O enable bit

•

Set the Local Init Done bit

Note:

NB# must be pulled up so the PCI 9080 issues

retries to all PCI accesses until the Local Init Done bit is

set in register (LOC:ECh) (refer to Table 4-59) by the

local processor.

The I2O enable bit in the Queue Status Register (LOC:

168h; Table 4-89) causes remapping of resources for

use in I2O mode. When this bit is set, all memory

mapped configuration registers (such as queue ports

40h and 44h) and Space 1 share PCIBAR0 (PCI:10h,

LOC:10h; Table 4-19). PCI accesses to offset 00h-FFh

of PCIBAR0 will result in accesses to the internal

configuration registers of the PCI 9080. Accesses above

offset FFh of PCIBAR0 will result in local space

accesses beginning at offset 100h from the Local

Space 1 Remap Register (LAS1BA, LOC:174h; Table 4-

46). Therefore space located at offset 00h-FFh from

LAS1BA is not addressable by way of PCIBAR0.

Programmer’s Note:

Because PCI accesses to offset

00h-FFh of PCIBAR0 result in internal configuration

accesses, Inbound Free MFAs must be greater than

FFh.

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