PCI9060ES datasheet(83/192 Pages) ETC

83 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 74

Version 1.02

4.5.11 (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register

Table 4-58. (INTCSR; PCI:68h, LOC:E8h) Interrupt Control/Status Register

Field

Description

Read

Write

Value after Reset

Enable Local Bus LSERR#. Value of 1 enables PCI 9080 to assert LSERR#

interrupt output when PCI bus Target Abort or Master Abort status bit is set in the

PCI Status configuration register.

Yes

Enable Local Bus LSERR# when PCI parity error occurs during PCI 9080 Master

Transfer or PCI 9080 Slave access or Outbound Free List FIFO Overflow Init.

Yes

Generate PCI Bus SERR#. When this bit is set to 0, writing a 1 generates a PCI

bus SERR#.

Yes

Mailbox Interrupt Enable. Value of 1 enables a Local Interrupt to be generated

when the PCI bus writes to Mailbox registers 0-3. To clear the Local Interrupt, the

Local master must read the Mailbox. Used in conjunction with Local interrupt

enable.

Yes

7:4

Reserved.

Yes

PCI Interrupt Enable. Value of 1 enables PCI interrupts.

Yes

PCI Doorbell Interrupt Enable. Value of 1 enables doorbell interrupts. Used in

conjunction with PCI interrupt enable. Clearing the doorbell interrupt bits that

caused the interrupt also clears the interrupt.

Yes

PCI Abort Interrupt Enable. Value of 1 enables a master abort or master detect of a

target abort to generate a PCI interrupt. Used in conjunction with PCI interrupt

enable. Clearing the abort status bits also clears the PCI interrupt.

Yes

PCI Local Interrupt Enable. Value of 1 enables a local interrupt input to generate a

PCI interrupt. Use in conjunction with PCI interrupt enable. Clearing the local bus

cause of the interrupt also clears the interrupt.

Yes

Retry Abort Enable. Value of 1 enables PCI 9080 to treat 256 Master consecutive

retries to a Target as a Target Abort. Value of 0 enables PCI 9080 to attempt

Master Retries indefinitely.

Note:

For diagnostic purposes only.

Yes

Value of 1 indicates PCI doorbell interrupt is active.

Yes

Value of 1 indicates PCI abort interrupt is active.

Yes

Value of 1 indicates local interrupt is active (LINTi#).

Yes

Local Interrupt Output Enable. Value of 1 enables local interrupt output.

Yes

Local Doorbell Interrupt Enable. Value of 1 enables doorbell interrupts. Used in

conjunction with Local interrupt enable. Clearing the local doorbell interrupt bits that

caused the interrupt also clears the interrupt.

Yes

Local DMA Channel 0 Interrupt Enable. Value of 1 enables DMA Channel 0

interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA status

bits also clears the interrupt.

Yes

Local DMA Channel 1 Interrupt Enable. Value of 1 enables DMA Channel 1

interrupts. Used in conjunction with Local interrupt enable. Clearing the DMA status

bits also clears the interrupt.

Yes

Value of 1 indicates local doorbell interrupt is active.

Yes

Value of 1 indicates DMA Ch 0 interrupt is active.

Yes

Value of 1 indicates DMA Ch 1 interrupt is active.

Yes

Value of 1 indicates BIST interrupt is active.

BIST (Built-In Self Test) interrupt is generated by writing 1 to bit 6 of the PCI

Configuration BIST register. Clearing bit 6 clears the interrupt. Refer to the BIST

Yes

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