PCI9060ES datasheet(48/192 Pages) ETC

48 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 39

Version 1.02

specifies that the number of message frames allocated

should be less than or equal to the number of entries in

a FIFO. (Refer to Figure 3-24 for additional information.)

Each inbound MFA is specified by I2O as the offset from

the start of shared local (IOP) memory region 0 to the

start of the message frame. Each outbound MFA is

specified as the offset from Host memory location

0x00000000h to the start of the message frame in

shared Host memory. Since the MFA is an actual

address, the message frames need not be contiguous.

IOP allocates and initializes inbound message frames in

shared

IOP

memory

using

any

suitable

memory

allocation technique.

Host

allocates

and

initializes

outbound message frames in shared Host memory using

any suitable memory allocation technique. Message

frames are a minimum of 64 bytes in length.

I2O uses a “push” (write preferred) memory model. That

means that the IOP will write messages and data to the

shared Host memory, and the Host will write messages

and data to shared IOP memory. Software should make

use of burst and DMA transfers whenever possible to

ensure efficient use of the PCI bus for message passing.

Additional

information

message

passing

implementation may be found in the

I2O Architecture

Specification v1.5.

3.13.4 Inbound Free List FIFO

The local processor allocates inbound message frames

in its shared memory and can place the address of a

free (available) message frame into the Inbound Free

List FIFO by writing its MFA into the FIFO location

pointed to by the Queue Base Register + Inbound Free

Head Pointer Register. The local processor must then

increment the Inbound Free Head Pointer Register.

A PCI master (Host or another IOP) can obtain the MFA

of a free message frame by reading the Inbound Queue

Port Address (40h of the first PCI Memory Base Address

frames are currently available, head and tail pointers are

equal), the MU returns a value of -1 (FFFFFFFFh). If

FIFO is not empty (head and tail pointers are not equal),

the MU reads the MFA pointed to by the Queue Base

value and increments the Inbound Free Tail Pointer

queue prefetching is enabled (QSR Register bit 3), the

next entry in the FIFO is read from the local bus into a

prefetch register. The prefetch register then provides the

data for the next PCI read from this queue, thus reducing

the number of PCI wait states.

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