PCI9060ES datasheet(67/192 Pages) ETC

67 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 58

Version 1.02

4.3.9 (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register

Table 4-18. (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register

Field

Description

Read

Write

Value after Reset

3:0

Value of 0 indicates device passed its test. Nonzero values indicate the device

failed. Device specific failure codes can be encoded in the nonzero value.

Yes

Local

5:4

Reserved. Device returns 0.

Yes

PCI writes a 1 to invoke BIST. Generates an interrupt to local bus. Local bus resets

the bit when BIST is complete. Software should fail device if BIST is not complete

after two seconds.

Refer to Runtime registers for interrupt control/status.

Yes

Returns 1 if the device supports BIST. Returns 0 if the device is not BIST

compatible.

Yes

Local

4.3.10 (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to

Local, Runtime, and DMA Registers

Table 4-19. (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime,

and DMA Registers

Field

Description

Read

Write

Value after Reset

Memory Space Indicator. Value of 0 indicates register maps into memory space.

Value of 1 indicates register maps into I/O space.

Note:

Hardcoded to 0.

Yes

2:1

Location of Register. Location values:

00—Locate anywhere in 32 bit memory address space

01—Locate below 1 MB memory address space

10—Locate anywhere in 64 bit memory address space

11—Reserved

Note:

Hardcoded to 0.

Yes

Prefetchable. Value of 1 indicates there are no side effects on reads. This bit has

no effect on the operation of the PCI 9080.

Note:

Hardcoded to 0.

Yes

7:4

Memory Base Address. Memory base address for access to Local, Runtime, and

DMA registers (default is 256 bytes).

Note:

Hardcoded to 0.

Yes

31:8

Memory Base Address. Memory base address for access to Local, Runtime, and

DMA registers.

Yes

Note:

For I2O, the Inbound message frame pool must reside in the address space pointed to by PCIBAR0. Message

Frame Address (MFA) is defined by I2O as the offset from this base address to the start of the message frame.

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