PCI9060ES datasheet(16/192 Pages) ETC

16 / 192 page

SECTION 2

PCI 9080

BUS OPERATION

©PLX Technology, Inc., 1997

Page 7

Version 1.02

REQ# for a minimum of two PCI clocks between bus

master ownership that includes a target disconnect.

The Direct Master Write Delay bits (bits [15:14]) of the

DMPBAM

(PCI:28h)(LOC:A8h)

can

programmed to delay the PCI 9080’s assertion of the

PCI REQ# signal during a Direct Master write cycle. This

bus clocks after the PCI 9080 has received its first write

data from the local master and is ready to begin the PCI

write transaction. This feature is useful in applications

where the local master is bursting and the local bus

clock is slower than the PCI bus clock. This allows write

data to accumulate in the PCI 9080’s Direct Master Write

FIFO, which provides for better PCI bus utilization.

2.2 LOCAL BUS CYCLES

PCI 9080 connects a PCI host bus to several local

processor bus types, as listed in Table 2-6. It operates in

one of three modes, selected through mode pins 9 and

10, corresponding to three bus types—C, J, and S.

Table 2-6. Local Processor Bus Types

Bit 9

Bit 10

Mode

Bus Type

32-bit nonmultiplexed

32-bit multiplexed

16-bit multiplexed

Reserved

—

2.2.1 Local Bus Arbitration

When PCI 9080 owns the local bus, both its LHOLD

output and LHOLDA input are asserted. When PCI 9080

samples BREQ asserted during a DMA transfer or

Direct Slave write transfer, it gives up the local bus

within two Lword transfers by de-asserting LHOLD and

floating its local bus outputs if BREQ is gated or

disabled, or if gating is enabled and the Local Bus

Latency Timer expires. The Local Arbiter can now grant

the local bus to another local master. After PCI 9080

samples that its LHOLDA is de-asserted and its local

pause timer is zero, it re-asserts LHOLD to request the

local bus. When the PCI 9080 receives LHOLDA, it

drives the bus and continues from where it left off.

2.2.2 Local Bus Direct Master

Local bus cycles can be continuous single or burst

cycles (programmable by way of the PCI 9080 internal

registers). As a local bus target, PCI 9080 allows access

to PCI 9080 internal registers and PCI bus.

In C and J modes, local bus direct master accesses to

the PCI 9080 must be for a 32 bit nonpipelined bus. In S

mode, local bus direct master accesses to the PCI 9080

must be for a 16 bit nonpipelined bus.

2.2.3 Local Bus Direct Slave

PCI Bus Master read/write to local bus (PCI 9080 is a

PCI bus target and local bus master).

2.2.3.1 Ready/Wait State Control

"!#

#! $ #

&&'

(

)

!! !+

-"%!.

! "

)

Figure 2-1. Wait States

If READYi# input is disabled, external READYi# input

has no effect on wait states for a local access. Wait

states between data cycles are generated internally by a

wait state counter. Wait state counter is initialized with its

configuration register value at the start of each data

access.

If READYi# is enabled, READYi# has no effect until the

wait state counter is 0. READYi# then controls the

number of additional wait states.

BTERM# input is not sampled until the wait state counter

is 0. BTERM# overrides READYi# when BTERM# is

asserted.

2.2.3.1.1 Wait State—Local Side

With Direct Master mode and accessing PCI 9080

registers (PCI 9080 local as slave):

•

PCI 9080 generates wait states with READYo#

•

Local processor generates wait states with WAITI#

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