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PCI9060ES Datasheet(PDF) 54 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 54 Page - List of Unclassifed Manufacturers |
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54 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 45 Version 1.02 Table 4-2. Register Differences between PCI 9080 and PCI 9060 (continued) Register PCI/Local Offset Bits Description 3 Mailbox Interrupt Enable 28 Mailbox 0 Interrupt Status 29 Mailbox 1 Interrupt Status 30 Mailbox 2 Interrupt Status INTCSR 68/E8 31 Mailbox 3 Interrupt Status PCIHIDR 70/F0 31:0 PCI Permanent Configuration ID Register PCIHREV 74/F4 7:0 PCI Permanent Revision ID Register 13 Write and Invalidate Mode for DMA Channel 0 transfers 13 DMA Write and Invalidate Mode 14 DMA EOT[1:0]# (End of Transfer) Input Pin Enable 15 DMA Stop Data Transfer Mode 16 DMA Clear Count Mode DMAMODE0 80/100 17 DMA Interrupt Select DMADPR0 90/110 0 DMA Descriptor Location Selector (PCI or Local) 13 DMA Write and Invalidate Mode 14 DMA EOT[1:0]# (End of Transfer) Input Pin Enable 15 DMA Stop Data Transfer Mode 16 DMA Clear Count Mode DMAMODE1 94/114 17 DMA Interrupt Select DMADPR1 A4/124 0 DMA Descriptor Location Selector (PCI or Local) DMACSR0 A8/128 4 DMA Channel 0 Done DMACSR1 A9/129 4 DMA Channel 1 Done DMATHR B0/130 15:0 Changed thresholds to accommodate 32 word write FIFOs OPQIS 30/B0 31:0 Outbound Post Queue Interrupt Status Register OPQIM 34/B4 31:0 Outbound Post Queue Interrupt Mask Register IQP 40 31:0 Inbound Queue Port OQP 44 31:0 Outbound Queue Port MQCR C0/140 31:0 Messaging Queue Configuration Register QBAR C4/144 31:0 Queue Base Address Register IFHPR C8/148 31:0 Inbound Free Head Pointer Register IFTPR CC/14C 31:0 Inbound Free Tail Pointer Register IPHPR D0/150 31:0 Inbound Post Head Pointer Register IPTPR D4/154 31:0 Inbound Post Tail Pointer Register OFHPR D8/158 31:0 Outbound Free Head Pointer Register OFTPR DC/15C 31:0 Outbound Free Tail Pointer Register OFHPR E0/160 31:0 Outbound Post Head Pointer Register OPTPR E4/164 31:0 Outbound Post Tail Pointer Register QSR E8/168 7:0 Queue Status/Control Register |
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