PCI9060ES datasheet(36/192 Pages) ETC

36 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 27

Version 1.02

If timer expires and PCI 9080 has not received LHOLDA,

PCI 9080 asserts BREQo. External bus logic can use

this as a signal to perform backoff.

A backoff cycle is device/bus architecture dependent.

External logic (arbiter) can assert the necessary signals

to cause the local master to release the local bus

(backoff). After backing off the local master, it can grant

the bus to the PCI 9080 (by asserting LHOLDA).

Once BREQo is asserted, READYo# for the current data

cycle will never be asserted (the local bus master must

perform backoff). When the PCI 9080 detects LHOLDA,

It proceeds with the PCI master to local bus access.

When this access is complete and the PCI 9080

releases the local bus, the external logic can release

backoff and the local master can resume the cycle that

was interrupted by the backoff cycle. The write FIFO of

the PCI 9080 retains all the data it has acknowledged

(i.e. the last data for which READYo# was asserted).

After the backoff condition ends, the local master

restarts the last cycle with ADS#. For writes, the data

following this ADS# should be the data that was not

acknowledged by the PCI 9080 prior to the backoff cycle

(for instance, the last data for which there was no

READYo# asserted).

If a PCI read cycle is completed when the local bus is

backed off, the local bus master receives that data if

local master restarts the same last cycle. (Data is not

read twice). A new read is performed, if the resumed

local bus cycle is not the same as the backed off cycle.

3.6.2.3.2 Software/Hardware Solution for Systems

without Backoff Capability

For adapters that do not support backoff, a possible

deadlock solution is as follows.

PCI host software, external local bus hardware, general

purpose output USERO and general purpose input

(USERI) can be used by PCI host software to prevent

deadlock. USERO can be set to request that the external

arbiter not grant the bus to any local bus master except

the PCI 9080. A status output from the local arbiter can

be connected to general purpose input USERI to

indicate that no local bus master owns the local bus. The

input can be read by the PCI host to determine that no

local bus master currently owns the local bus. PCI host

can then perform a direct slave access. When the host is

done, it clears USERO. For devices that support

preempt, USERO can be used to preempt the current

bus master device. The current local bus master device

completes its current cycle and gives up the local bus

(de-asserts LHOLD).

3.6.2.3.3 Software Solutions to Deadlock

PCI host software and local bus software can use a

combination of mailbox registers, doorbell registers,

interrupts, direct local to PCI accesses and direct PCI to

local accesses to avoid deadlock.

3.6.2.4 Direct Slave Lock

PCI 9080 supports direct PCI to local bus exclusive

accesses (locked atomic operations). A PCI locked

operation to local bus results in the entire address space

0, space 1 and expansion ROM space being locked until

they are released by the PCI bus master. PCI 9080

asserts LLOCKo# during the first clock of an atomic

operation (address cycle) and de-asserts it a minimum of

one clock, following the last bus access for the atomic

operation. LLOCKo# is de-asserted after the PCI 9080

detects PCI FRAME# and PCI LOCK# de-asserted at

the same time. Refer to the timing diagrams in Section 8,

“Timing Diagrams.” Locked operations are enabled or

disabled with the Local Bus Region Descriptor Register

for PCI to local accesses.

It is the responsibility of external arbitration logic to

monitor the LLOCKo# pin and enforce the meaning for

an atomic operation. For example, if a local master

initiates a locked operation, the local arbiter may choose

to not grant use of the local bus to other masters until

the locked operation is complete.

3.6.3 Direct Slave Priority

Direct Slave accesses have higher priority than DMA

accesses.

Direct Slave accesses preempt DMA transfers. When

the PCI 9080 DMA controller owns the local bus, its

LHOLD output and LHOLDA input are asserted and its

LDSHOLD output is de-asserted. When a Direct Slave

access occurs, PCI 9080 gives up the local bus within

two Lword transfers by de-asserting LHOLD and floating

its local bus outputs. After the PCI 9080 samples its

LHOLDA input de-asserted, it requests the local bus for

a Direct Slave transfer by asserting LHOLD and

LDSHOLD. When the PCI 9080 receives LHOLDA, it

drives the bus and performs the Direct Slave transfer.

Upon completion of the Direct Slave transfer, PCI 9080

gives up the local bus by de-asserting both LHOLD and

LDSHOLD and floating its local bus outputs. After the

PCI 9080 samples its LHOLDA de-asserted and its local

pause timer is zero, it requests the local bus for a DMA

transfer by re-asserting LHOLD. When it receives

LHOLDA, it drives the bus and continues with the DMA

transfer.

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