PCI9060ES datasheet(28/192 Pages) ETC

28 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 19

Version 1.02

•

PCI Configuration Address Register for Direct

Master to PCI IO/CFG

•

PCI Base Address

3.6.1.1 Decode

The Range register specifies the local address bits to

use for decoding a Local to PCI access. The local

processor can perform only memory cycles. Therefore,

the Local Base Address for Direct Master to PCI Memory

space and the Local Base Address for Direct Master to

PCI IO/CFG Register is used to decode an access to

PCI I/O space or PCI bus configuration cycle access.

3.6.1.2 FIFOs

For Direct Master memory access to the PCI bus, PCI

9080 has a 32 Lword (128 byte) write FIFO and a 16

Lword (64 byte) read FIFO. FIFOs enable the local bus

to operate independently of the PCI bus and allows high-

performance bursting on local and PCI buses. In a Direct

Master Write, the local processor (Master) writes data to

PCI (Slave). In a Direct Master Read, the local processor

(Master) reads data from PCI (Slave). Figure 3-6 and

Figure 3-7 illustrate the FIFOs during a Direct Master

Write and Read.

&(); <)

)=>) ;

; >; );

; ,<; >

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Figure 3-6. Direct Master Write

&(); <);

)=>) ; ;

; >; ,<

; )

Figure 3-7. Direct Master Read

3.6.1.3 Memory Access

The local processor can read or write to the PCI

memory. PCI 9080 converts the local read/write access.

The Local Address space starts from the Direct Master

Local Base Address up to the range. Remap (PCI Base

Address) defines the PCI starting address.

Writes—PCI 9080 continues to accept writes and return

READYo# until write FIFO is full. It then holds off

READYo# until space becomes available in the write

FIFO. A programmable Direct Master FIFO “almost full”

status output is provided (DMPAF#).

Reads—PCI 9080 holds off READYo# while gathering

an Lword from the PCI bus. Programmable prefetch

modes are available if prefetch is enabled: prefetch, 4, 8,

16, or continuous until Direct Master cycle ends. The

read cycle is terminated when the local BLAST# input is

asserted. Unused read data is flushed from the FIFO.

PCI 9080 does not prefetch read data for single cycle

Direct Master reads (local BLAST# input asserted during

first data phase). In this case, PCI 9080 reads a single

PCI Lword.

For Direct Master single cycle reads, PCI 9080 asserts

the same PCI bus byte enables as asserted on the local

bus.

For multiple cycle reads, PCI 9080 reads entire Lwords

(all PCI byte enables are asserted), regardless of local

byte enables.

If the prefetch limit bit DMPBAM (PCI:28h)(LOC:A8h)

(refer to Table 4-43[11]) is enabled, PCI 9080 does not

prefetch past a 4K boundary. Also, the local side must

not cross a 4K boundary during a burst read.

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