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PCI9060ES Datasheet(PDF) 82 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 82 Page - List of Unclassifed Manufacturers |
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82 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 73 Version 1.02 4.5.6 (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 Table 4-53. (MBOX5; PCI:54h, LOC:D4h) Mailbox Register 5 Field Description Read Write Value after Reset 31:0 32 Bit Mailbox Register. Yes Yes 0 4.5.7 (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 Table 4-54. (MBOX6; PCI:58h, LOC:D8h) Mailbox Register 6 Field Description Read Write Value after Reset 31:0 32 Bit Mailbox Register. Yes Yes 0 4.5.8 (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7 Table 4-55. (MBOX7; PCI:5Ch, LOC:DCh) Mailbox Register 7 Field Description Read Write Value after Reset 31:0 32 Bit Mailbox Register. Yes Yes 0 4.5.9 (P2LDBELL; PCI:60h, LOC:E0h) PCI to Local Doorbell Register Table 4-56. (P2LDBELL; PCI:60h, LOC:E0h) PCI to Local Doorbell Register Field Description Read Write Value after Reset 31:0 Doorbell Register. A PCI master can write to this register and generate a local interrupt to the local processor. The local processor can then read this register to determine which doorbell bit was asserted. PCI master sets a doorbell by writing 1 to a particular bit. The local processor can clear a doorbell bit by writing 1 to that bit position. Yes Yes/Clr 0 4.5.10 (L2PDBELL; PCI:64h, LOC:E4h) Local to PCI Doorbell Register Table 4-57. (L2PDBELL; PCI:64h, LOC:E4h) Local to PCI Doorbell Register Field Description Read Write Value after Reset 31:0 Doorbell Register. The local processor can write to this register and generate a PCI interrupt. A PCI master can then read this register to determine which doorbell bit was asserted. The local processor sets a doorbell by writing 1 to a particular bit. PCI master can clear a doorbell bit by writing 1 to that bit position. Yes Yes/Clr 0 |
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