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PCI9060ES Datasheet(PDF) 64 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 64 Page - List of Unclassifed Manufacturers |
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64 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 55 Version 1.02 4.3 PCI CONFIGURATION REGISTERS All registers may be written to or read from in byte, word, or Lword accesses. 4.3.1 (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register Table 4-10. (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register Field Description Read Write Value after Reset 15:0 Vendor ID. Identifies device manufacturer. Defaults to the PCI SIG issued vendor ID of PLX (10B5h) if no serial EEPROM is present and pin NB# (no local bus initialization) is asserted low. Yes Local/ Serial EEPROM 10B5h or 0 31:16 Device ID. Identifies the particular device. Defaults to the PLX part number for PCI interface chip (PCI 9080) if no serial EEPROM is present and pin NB# (no local bus initialization) is asserted low. Yes Local/ Serial EEPROM 9080h or 0 4.3.2 (PCICR; PCI:04h, LOC:04h) PCI Command Register Table 4-11. (PCICR; PCI:04h, LOC:04h) PCI Command Register Field Description Read Write Value after Reset 0 I/O Space. Value of 1 allows device to respond to I/O space accesses. Value of 0 disables device from responding to I/O space accesses. Yes Yes 0 1 Memory Space. Value of 1 allows device to respond to memory space accesses. Value of 0 disables device from responding to memory space accesses. Yes Yes 0 2 Master Enable. Value of 1 allows device to behave as a bus master. Value of 0 disables device from generating bus master accesses. This bit must be set for the PCI 9080 to perform Direct Master or DMA cycles. Yes Yes 0 3 Special Cycle. (This bit is not supported.) Yes No 0 4 Memory Write/Invalidate Enable Bit. Value of 1 enables memory write/invalidate. Value of 0 disables memory write/invalidate. (Refer to the DMA Mode Registers (DM, DMAMODE0, and DMAMODE1) bit 13.) (Refer to Table 4-43[13], Table 4-62[13], and Table 4-67[13], respectively.) Yes Yes 0 5 VGA Palette Snoop. (This bit is not supported.) Yes No 0 6 Parity Error Response. Value of 0 indicates a parity error is ignored and operation continues. Value of 1 indicates parity checking is enabled. Yes Yes 0 7 Wait Cycle Control. Controls whether the device performs address/data stepping. Value of 0 indicates device never does stepping. Value of 1 indicates device always does stepping. Note: Hardcoded to 0. Yes No 0 8 SERR# Enable. Value of 1 enables SERR# driver. Value of 0 disables SERR# driver. Yes Yes 0 9 Fast Back-to-Back Enable. Indicates type of fast back-to-back transfers Master can perform on bus. Value of 1 indicates fast back-to-back transfers can occur to any agent on bus. Value of 0 indicates fast back-to-back transfers can only occur to same agent as previous cycle. Yes No 0 15:10 Reserved. Yes No 0 |
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