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PCI9060ES Datasheet(PDF) 65 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 65 Page - List of Unclassifed Manufacturers |
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65 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 56 Version 1.02 4.3.3 (PCISR; PCI:06h, LOC:06h) PCI Status Register Table 4-12. (PCISR; PCI:06h, LOC:06h) PCI Status Register Field Description Read Write Value after Reset 5:0 Reserved. Yes No 0 6 If high, supports User Definable Features. This bit can only be written from the local side. It is read-only from the PCI side. Yes Local 0 7 Fast Back-to-Back Capable. When this bit is set to 1, it indicates the adapter can accept fast back-to-back transactions. Value of 0 indicates adapter cannot. Yes No 1 8 Master Data Parity Error Detected. This bit is set to 1 when three conditions are met: 1) the PCI 9080 asserted PERR# itself or observed PERR# asserted; 2) the PCI 9080 was the bus master for the operation in which the error occurred; 3) the Parity Error Response bit in the Command Register is set. Writing 1 to this bit clears the bit (0). Yes Yes/Clr 0 10:9 DEVSEL Timing. Indicates timing for DEVSEL# assertion. Value of 01 indicates a medium decode. Note: Hardcoded to 01. Yes No 01 11 Target Abort. When this bit is set to 1, this bit indicates the PCI 9080 has signaled a target abort. Writing 1 to this bit clears the bit (0). Yes Yes/Clr 0 12 Received Target Abort. When set to 1, this bit indicates the PCI 9080 has received a target abort signal. Writing 1 to this bit clears the bit (0). Yes Yes/Clr 0 13 Master Abort. When set to 1, this bit indicates the PCI 9080 has generated a master abort signal. Writing 1 to this bit clears the bit (0). Yes Yes/Clr 0 14 Signaled System Error. When set to 1, this bit indicates the PCI 9080 has reported a system error on the SERR# signal. Writing 1 to this bit clears the bit (0). Yes Yes/Clr 0 15 Detected Parity Error. When set to 1, this bit indicates the PCI 9080 has detected a PCI bus parity error, even if parity error handling is disabled (the Parity Error Response bit in the Command Register is clear). One of three conditions can cause this bit to be set. 1) the PCI 9080 detected a parity error during a PCI address phase; 2) the PCI 9080 detected a data parity error when it was the target of a write; 3) the PCI 9080 detected a data parity error when performing a master read operation. Writing 1 to this bit clears the bit (0). Yes Yes/Clr 0 4.3.4 (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register Table 4-13. (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register Field Description Read Write Value after Reset 7:0 Revision ID. Silicon revision of PCI 9080. Yes Local/ Serial EEPROM Current Rev # |
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