PCI9060ES datasheet(92/192 Pages) ETC

92 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 83

Version 1.02

4.6.14 (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register

Table 4-74. (DMATHR; PCI:B0h, LOC:130h) DMA Threshold Register

Field

Description

Read

Write

Value after Reset

3:0

DMA Channel 0 PCI to Local Almost Full (C0PLAF). Number of full entries (divided

by two, minus one) in FIFO before requesting local bus for writes.

(C0PLAF+1) + (C0PLAE+1) should be

≤ FIFO Depth of 32.

Yes

7:4

DMA Channel 0 Local to PCI Almost Empty (C0LPAE). Number of empty entries

(divided by two, minus one) in FIFO before requesting local bus for reads.

(C0LPAF+1) + (C0LPAE+1) should be

≤ FIFO depth of 32.

Yes

11:8

DMA Channel 0 Local to PCI Almost Full (C0LPAF). Number of full entries (divided

by two, minus one) in FIFO before requesting local bus for writes.

Yes

15:12

DMA Channel 0 PCI to Local Almost Empty (C0PLAE). Number of empty entries

(divided by two, minus one) in FIFO before requesting local bus for reads.

Yes

19:16

DMA Channel 1 PCI to Local Almost Full (C1PLAF). Number of full entries (divided

by two, minus one) in FIFO before requesting local bus for writes.

(C1PLAF+1) + (C1PLAE+1) should be

≤ FIFO depth of 16.

Yes

23:20

DMA Channel 1 Local to PCI Almost Empty (C1LPAE). Number of empty entries

(divided by two, minus one) in FIFO before requesting local bus for reads.

(C1PLAF+1) + (C1PLAE+1) should be

≤ FIFO depth of 16.

Yes

27:24

DMA Channel 1 Local to PCI Almost Full (C1LPAF). Number of full entries (divided

by two, minus one) in FIFO before requesting local bus for writes.

Yes

31:28

DMA Channel 1 PCI to Local Almost Empty (C1PLAE). Number of empty entries

(divided by two, minus one) in FIFO before requesting local bus for reads.

Yes

Note:

If the number of entries needed is x, then value is one less than half the number of entries (that is, x/2 – 1).

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