PCI9060ES datasheet(35/192 Pages) ETC

35 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 26

Version 1.02

Example 2—A 1 MB Local Address Space 12300000h

through 123FFFFFh is accessible from the PCI bus at

PCI addresses 78900000h through 789FFFFFh.

Local initialization software sets the Range and

Local Base Address Registers as follows:

•

Range—FFF00000h (1 MB, decode the upper

12 PCI address bits)

•

Local Base Address (remap)—123XXXXXh

(Local Base Address for PCI to local accesses)

(bit 0, the Space Enable bit, must be set to 1 to

be recognized by the host)

PCI Initialization software writes all ones to the PCI

Base Address, then reads it back again.

•

PCI 9080 returns a value FFF00000h. The PCI

software then writes to PCI Base Address

•

PCI Base Address—789XXXXXh (PCI Base

Address for access to Local Address space)

For PCI direct access to the local bus, PCI 9080 has a

32 Lword (128 byte) write FIFO and a 16 Lword (64

byte) read FIFO. FIFOs enable the local bus to operate

independently of the PCI bus. PCI 9080 can be

programmed to return a RETRY response or to throttle

TRDY# for any PCI bus transaction attempting to write to

the PCI 9080 local bus when the FIFO is full.

For PCI read transactions from the PCI 9080 local bus,

PCI 9080 holds off TRDY# while gathering the local bus

Lword to be returned. For read accesses mapped to the

PCI memory space, PCI 9080 prefetches up to 16

Lwords (has continuous prefetch mode) from the local

bus. Unused read data is flushed from the FIFO. For

read accesses mapped to the PCI I/O space, PCI 9080

does not prefetch read data. Rather, it breaks each read

of the burst cycle into a single address/data cycle on the

local bus.

The period of time the PCI 9080 holds off TRDY# can be

programmed, Target Retry Timer, in the Local Bus

Region Descriptor Register (refer to Table 4-39). PCI

9080 issues a RETRY to the PCI bus transaction master

when the programmed time period expires. This occurs

when the PCI 9080 cannot gain control of the local bus

and return TRDY# within the programmed time period.

3.6.2.3 Deadlock and BREQo

A deadlock situation can occur when a master on the

PCI bus wants to access the PCI 9080 local bus at the

same time a master on the local PCI 9080 bus wants to

access the PCI bus. Two types of deadlock situations

can occur:

•

Partial Deadlock—A master on the local bus is

performing a direct bus master access to a PCI bus

device other than the PCI bus device that is

concurrently trying to access the local bus.

•

Full Deadlock—A master on the local bus is

performing a direct bus master access to the same

PCI bus device that is concurrently trying to access

the local bus.

This applies only to direct (“pass through”) master and

slave accesses through the PCI 9080. Deadlock will not

occur in transfers through the PCI 9080 DMA controller

or the mailboxes.

For partial deadlock, the PCI access to the local bus

times

out

(the

Target

Retry

Timer,

which

programmable through the Local Bus Region Descriptor

responds with a PCI RETRY. PCI specification requires

that a PCI master release its request for the PCI bus

(de-asserts REQ#) for a minimum of two PCI clocks after

receiving a RETRY. This allows the PCI bus arbiter to

grant the PCI bus to the PCI 9080 so that it can

complete its direct master access and free up the local

bus. Possible solutions are described below for cases in

which the PCI bus arbiter does not function as described

(PCI bus architecture dependent), waiting for a time-out

is undesirable, or a full deadlock condition exists.

For full deadlock, the only solution is to back off the local

master.

3.6.2.3.1 Backoff

PCI 9080 contains a pin (BREQo) that indicates a

possible deadlock condition exists. PCI 9080 starts the

BREQo timer (programmable through registers) when it

detects the following conditions:

•

A master on the PCI bus is trying to access memory

or an I/O device on the local bus and is not gaining

access (for example, LHOLDA not received).

•

A master on the local bus is performing a direct bus

master read access to the PCI bus or a master on

the local bus is performing a direct bus master write

access to the PCI bus and the PCI 9080’s direct

master write FIFO cannot accept another write cycle.

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