PCI9060ES datasheet(73/192 Pages) ETC

73 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 64

Version 1.02

4.4.3 (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register

Table 4-35. (MARBR; PCI:08h or ACh, LOC:88h or 12Ch) Mode/Arbitration Register

Field

Description

Read

Write

Value after Reset

7:0

Local Bus Latency Timer. Number of local bus clock cycles before negating HOLD

and releasing the local bus. This timer is also used with bit 27 to delay BREQ input

to give up the local bus only when this timer expires.

Yes

15:8

Local Bus Pause Timer. Number of local bus clock cycles before reasserting HOLD

after releasing the local bus.

Note:

Applicable only to DMA operation.

Yes

Local Bus Latency Timer Enable. Value of 1 enables latency timer.

Yes

Local Bus Pause Timer Enable. Value of 1 enables pause timer.

Yes

Local Bus BREQ Enable. Value of 1 enables local bus BREQ input. When the

BREQ input is active, PCI 9080 negates HOLD and releases the local bus.

Yes

20:19

DMA Channel Priority. Value of 00 indicates a rotational priority scheme. Value of

01 indicates Channel 0 has priority. Value of 10 indicates Channel 1 has priority.

Value of 11 is reserved.

Yes

Local Bus Direct Slave Give up Bus Mode. When set to 1, PCI 9080 negates HOLD

and releases the local bus when the Direct Slave write FIFO becomes empty during

a Direct Slave write or when the Direct Slave read FIFO becomes full during a

Direct Slave read.

Yes

Direct Slave LLOCKo# Enable. Value of 1 enables PCI Direct Slave locked

sequences. Value of 0 disables Direct Slave locked sequences.

Yes

PCI Request Mode. Value of 1 causes PCI 9080 to negate REQ when it asserts

FRAME during a master cycle. Value of 0 causes PCI 9080 to leave REQ asserted

for the entire bus master cycle.

Yes

PCI Rev 2.1 Mode. When set to 1, PCI 9080 operates in Delayed Transaction mode

for Direct Slave Reads. PCI 9080 issues a RETRY and prefetches the read data.

Yes

PCI Read No Write Mode. Value of 1 forces a retry on writes if read is pending.

Value of 0 allows writes to occur while read is pending.

Yes

PCI Read with Write Flush Mode. Value of 1 submits a request to flush a pending

read cycle if a write cycle is detected. Value of 0 submits a request to not effect

pending reads when a write cycle occurs (PCI v2.1 compatible).

Yes

Gate the Local Bus Latency Timer with BREQ. If this bit is set to 0, PCI 9080 gives

up the local bus during Direct Slave or DMA transfer after the current cycle (if

enabled and BREQ is sampled). If this bit is set to 1, PCI 9080 gives up the local

bus only (if BREQ is sampled) and the Local Bus Latency Timer is enabled and

expired during Direct Slave or DMA transfer.

Yes

PCI Read No Flush Mode. Value of 1 submits request to not flush the read FIFO

if PCI read cycle completes (Read Ahead mode).

Value of 0 submits request to flush read FIFO if PCI read cycle completes.

Yes

If set to 0, reads from the PCI Configuration Register address 00h and returns the

Device ID and Vendor ID. If set to 1, reads from the PCI Configuration Register

address 00h and returns the Subsystem ID and Subsystem Vendor ID.

Yes

31:30

Reserved.

Yes

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