PCI9060ES datasheet(98/192 Pages) ETC

98 / 192 page

SECTION 5

PCI 9080

PIN DESCRIPTION

©PLX Technology, Inc., 1997

Page 89

Version 1.02

5. PIN DESCRIPTION

5.1 PIN SUMMARY

The tables in this section describe PCI 9080 pins. Table

5-2 through Table 5-5 provide pin information common

to all three local bus modes of operation (that is, C, J,

and S modes):

•

Power and Ground Pin Description

•

Serial EEPROM Interface Pin Description

•

PCI System Bus Interface Pin Description

•

Local Bus Mode and Processor Independent

Interface Pin Description

The pins in Table 5-6 through Table 5-8 correspond to

the local bus modes of the PCI 9080:

•

C Bus Mode Interface Pin Description (32-bit

address/32-bit data, nonmultiplexed)

•

J Bus Mode Interface Pin Description (32-bit

address/32-bit data, multiplexed)

•

S Bus Mode Interface Pin Description (32-bit

address/16-bit data, multiplexed)

The following pins have internal pull-ups:

ADMODE, BIGEND#, BTERM#, DREQ[1:0]#, EEDO,

EESEL, LINTi#, LLOCK#, LRESETi#, NB#, READYi#,

S[2:0], SHORT#, and WAITI#.

The following pins have internal pull-downs:

BREQ, LHOLDA, TEST, and USERI.

For a visual view of the chip pin out, refer to Figure 7-3

in Section 7.3, “9080 Pin Out (S, J, and C Modes).”

Table 5-1 lists the abbreviations used in this section to

represent the various pin types.

Table 5-1. Pin Type Abbreviations

Abbreviation

Pin Type

I/O

Input and output pin

Input pin only

Output pin only

Tri-state pin

Open collector pin

Totem pole pin

STS

Sustained tri-state pin, driven high for one CLK

before float

DTS

Driven tri-state pin, driven high for one-half CLK

before float

All local bus internal pull-ups go through a 2 k

Ω resistor.

All local bus internal pull-downs go through a 100 k

Ω

resistor.

All local tri-state I/O pins should have external pull-ups

(use 3 k

Ω - 10 kΩ).

Unspecified pins are not connected.

Note:

For PCI Pins, DO NOT pull up or down any pins

unless the PCI 9080 is being used in an embedded

design. Refer to the PCI Local Bus Specification, v2.1,

page 123.

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