PCI9060ES datasheet(102/192 Pages) ETC

102 / 192 page

SECTION 5

PCI 9080

PIN DESCRIPTION

©PLX Technology, Inc., 1997

Page 93

Version 1.02

Table 5-5. Local Bus Mode and Processor Independent Interface Pin Description (continued)

Symbol

Signal Name

Total

Pins

Type

Number

Function

LSERR#

System Error

Interrupt Output

8 mA

Synchronous level output that is asserted when the PCI bus Target

Abort or Master Abort status bit is set in the PCI Status configuration

enabling LSERR# interrupts through the interrupt/control status

creates an edge if an interrupt condition still exists or a new interrupt

condition occurs.

MODE[1:0]

Bus Mode

9, 10

Selects the bus operation mode of the PCI 9080:

Bit 1

Bit 0

Bus Mode

00C

01J

10S

Reserved

NB#

No Local Bus

Initialization

Externally forces Local Init Done bit in the Init Control Register to 1.

Init Done bit is also programmable through local bus configuration

accesses. PCI 9080 issues RETRYs to all PCI accesses until Local

Init Done bit is set. If this bit is not going to be set by a local

processor, tie NB# low.

PCHK#

Data Parity Check

8 mA

Parity is checked for writes to the PCI 9080 or reads by the PCI 9080.

Parity is checked for each byte lane with its byte enable asserted.

Asserted in the clock cycle following the data being checked if a parity

error is detected.

S[2:0]

Address Select

17-19

If ADMODE is high, internal PCI 9080 registers are selected when

LA[31:29] match S[2:0].

If ADMODE is low, the internal PCI 9080 registers are selected when

S0 is asserted low.

USERI

User Input

General purpose input that can be read from the PCI 9080

configuration registers.

USERO

User Output

12 mA

General purpose output controlled from the PCI 9080 configuration

registers.

WAITI#

Wait Input

Can be asserted to cause the PCI 9080 to insert wait states for local

direct master accesses to the PCI bus. Can be thought of as a ready

input for direct master accesses.

WAITO#

Wait Out

8 mA

149

Indicates the PCI 9080 programmable wait state generator status.

WAITO# is asserted when wait states are being caused by the

internal wait state generator. Can be thought of as an output providing

ready out status.

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