PCI9060ES datasheet(106/192 Pages) ETC

106 / 192 page

SECTION 5

PCI 9080

PIN DESCRIPTION

©PLX Technology, Inc., 1997

Page 97

Version 1.02

Table 5-7. J Bus Mode Interface Pin Description (continued)

J Mode Bus

Symbol

Signal Name

Total

Pins

Type

Number

Function

LBE[3:0]#

Byte Enables

I/O

12 mA

139-142

Byte enables are encoded based on configured bus width as follows:

32-Bit Bus:

For a 32-bit bus, the four byte enables indicate which of the four bytes

are active during a data cycle:

BE3# Byte Enable 3—LAD[31:24]

BE2# Byte Enable 2—LAD[23:16]

BE1# Byte Enable 1—LAD[15:8]

BE0# Byte Enable 0—LAD[7:0]

16-Bit Bus:

For a 16-bit bus, BE3#, BE1# and BE0# are encoded to provide

BHE#, LA1, and BLE#, respectively:

BE3# Byte High Enable (BHE#)—LAD[15:8]

BE2# not used

BE1# Address bit 1 (LA1)

BE0# Byte Low Enable (BLE#)—LAD[7:0]

8-Bit Bus:

For an 8-bit bus, BE1# and BE0# are encoded to provide LA1and

LA0, respectively:

BE3# not used

BE2# not used

BE1# Address bit 1 (LA1)

BE0# Address bit 0 (LA0)

LCLK

System Clock

160

Local clock input.

LHOLD

Hold Request

8 mA

158

Asserted to request use of the local bus. The local bus arbiter asserts

LHOLDA when control is granted.

LHOLDA

Hold Acknowledge

159

Asserted by the local bus arbiter when control is granted in response

to LHOLD. The bus should not be granted to PCI 9080 unless

requested by LHOLD.

LLOCK#

Bus Lock

153

Indicates an atomic operation that may require multiple transactions

to complete. Used by the PCI 9080 for direct local access to the PCI

bus.

LRESETo#

Local Bus Reset Out

8 mA

Asserted when the PCI 9080 chip is reset.

READYi#

Ready In

147

When the PCI 9080 is a bus master, READYi# is used to indicate

read data on the bus is valid or a write data transfer is complete.

READYi# is used in conjunction with the PCI 9080 programmable wait

state generator.

READYo#

Ready Out

DTS

8 mA

148

When a local bus access is made to the PCI 9080, indicates that read

data on the bus is valid or that a write data transfer is complete.

READYo# can be connected to READYi#.

EOT0#

End of Transfer for

DMA Ch 0

Terminates the current DMA Ch 0 transfer.

EOT1#

End of Transfer for

DMA Ch 1

Terminates the current DMA Ch 1 transfer.

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