PCI9060ES datasheet(107/192 Pages) ETC

107 / 192 page

SECTION 5

PCI 9080

PIN DESCRIPTION

©PLX Technology, Inc., 1997

Page 98

Version 1.02

5.5 S BUS MODE PIN OUT

Table 5-8. S Bus Mode Interface Pin Description

S Bus Mode

Symbol

Signal Name

Total

Pins

Type

Number

Function

ALE

Address Latch

Enable

8 mA

161

Asserted during the address phase and negated before the data

phase.

AS#

Address Strobe

I/O

12 mA

154

Indicates valid address and the start of a new bus access. Asserted

for the first clock of a bus access.

BLAST#

Burst Last

I/O

8 mA

155

Signal driven by the current local bus master to indicate the last

transfer in a bus access.

BTERM#

Burst Terminate

146

For processors that burst up to eight words and do not use BTERM#

input. If Bterm is disabled through the PCI 9080 configuration

registers, PCI 9080 also bursts up to eight words. If enabled, PCI

9080 continues to burst until a BTERM# input is asserted. BTERM#

breaks up a burst cycle and causes another address cycle to occur.

Used in conjunction with the PCI 9080 programmable wait state

generator.

DEN#

Data Enable

12 mA

145

Used in conjunction with DT/R# to provide control for data

transceivers attached to the local bus.

DT/R#

Data

Transmit/Receive

12 mA

138

Used in conjunction with DEN# to provide control for data transceivers

attached to the local bus. When asserted, the signal indicates the PCI

9080 is receiving data.

LA[31:16]

Address Bus

I/O

8 mA

136, 135,

133-125,

122-118

Carries the upper 16 bits of the address.

LABS[3:1]

Address Bus Burst

I/O

8 mA

162-164

Carries the word address of the 32 bit memory address. These bits

are incremented during a burst access.

LAD[15:1],D0

Address/Data Bus

I/O

8 mA

117-115,

113-106,

103-99

During the address phase, carries the lower physical address bits.

During the data phase, carries 16 bits of data.

LBE[1:0]#

Byte Enables

I/O

12 mA

141,142

Indicate which of the two bytes are active during a data cycle.

LCLK

Local Clock

160

Local clock input.

Note:

For i960®S processor systems, CLK2 input. i960®S

processor’s RESET# input must be connected to PCI 9080

LRESETo# output. This enables PCI 9080 to determine the phase of

the 2x clock processor.

LHOLD

Hold Request

8 mA

158

Asserted to request use of the local bus. The local bus arbiter asserts

LHOLDA when control is granted.

LHOLDA

Hold Acknowledge

159

Asserted by the local bus arbiter when control is granted in response

to LHOLD. The bus should not be granted to the PCI 9080 unless

requested by LHOLD.

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