PCI9060ES datasheet(100/192 Pages) ETC

100 / 192 page

SECTION 5

PCI 9080

PIN DESCRIPTION

©PLX Technology, Inc., 1997

Page 91

Version 1.02

Table 5-4. PCI System Bus Interface Pin Description

Symbol

Signal Name

Total

Pins

Type

Number

Function

AD[31:0]

Address and Data

I/O

PCI

32-36, 39-44,

46-47, 76-81,

84-89, 91-97

All multiplexed on the same PCI pins. A bus transaction consists of an

address phase followed by one or more data phases. PCI 9080

supports both read and write bursts.

C/BE[3:0]#

Bus Command and

Byte Enables

I/O

PCI

70-73

All multiplexed on the same PCI pins. During the address phase of a

transaction, C/BE[3:0]# defines the bus command. During the data

phase C/BE[3:0]# are used as Byte Enables. Refer to PCI spec for

further detail if needed.

CLK

Clock

Provides timing for all transactions on PCI and is an input to every

PCI device. PCI operates up to 33 MHz.

DEVSEL#

Device Select

I/O

STS

PCI

When actively driven, indicates the driving device has decoded its

address as the target of the current access. As an input, indicates

whether any device on the bus is selected.

FRAME#

Cycle Frame

I/O

STS

PCI

Driven by the current master to indicate the beginning and duration of

an access. FRAME# is asserted to indicate a bus transaction is

beginning. While FRAME# is asserted, data transfers continue. When

FRAME# is negated, the transaction is in the final data phase.

GNT#

Grant

Indicates to the agent that access to the bus is granted. Every master

has its own REQ# and GNT#.

IDSEL

Initialization Device

Select

Used as a chip select during configuration read and write

transactions.

INTA#

Interrupt A

PCI

Used to request an interrupt.

IRDY#

Initiator Ready

I/O

STS

PCI

Indicates the ability of the initiating agent (bus master) to complete the

current data phase of the transaction.

LOCK#

Lock

I/O

STS

PCI

Indicates an atomic operation that may require multiple transactions

to complete.

PAR

Parity

I/O

PCI

Even parity across AD[31:0] and C/BE[3:0]#. Parity generation is

required by all PCI agents. PAR is stable and valid one clock after the

address phase. For data phases, PAR is stable and valid one clock

after either IRDY# is asserted on a write transaction or TRDY# is

asserted on a read transaction. Once PAR is valid, it remains valid

until one clock after the completion of the current data phase.

PERR#

Parity Error

I/O

STS

PCI

Reporting of data parity errors during all PCI transactions, except

during a Special Cycle.

REQ#

Request

PCI

Indicates to the arbiter that this agent needs to use the bus. Every

master has its own GNT# and REQ#.

RST#

Reset

Used to bring PCI-specific registers, sequencers and signals to a

consistent state.

SERR#

Systems Error

PCI

Reports address parity errors, data parity errors on the Special Cycle

command, or any other system error where the result will be

catastrophic.

STOP#

Stop

I/O

STS

PCI

Indicates the current target is requesting the master to stop the

current transaction.

TRDY#

Target Ready

I/O

STS

PCI

Indicates the ability of the target agent (selected device) to complete

the current data phase of the transaction.

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