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PCI9060ES Datasheet(PDF) 29 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 29 Page - List of Unclassifed Manufacturers |
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29 / 192 page ![]() SECTION 3 PCI 9080 FUNCTIONAL DESCRIPTION ©PLX Technology, Inc., 1997 Page 20 Version 1.02 PCI 9080 never prefetches beyond the region specified for direct master accesses. 3.6.1.4 IO/CFG Access When a Local Direct Master I/O access to the PCI bus is made, the PCI Configuration Address Register’s Configuration Enable bit determines if an I/O or configuration access is to be made to the PCI bus. Local burst accesses are broken into single PCI I/O address/data cycles. PCI 9080 does not prefetch read data for I/O and CFG reads. For Direct Master I/O or Configuration cycles, PCI 9080 asserts the same PCI bus byte enables as asserted on the local bus. 3.6.1.5 I/O If the Configuration Enable bit is clear, a single I/O access is made to the PCI bus. The local address, remapped decode address bits and the local byte enables are encoded to provide the address and is output with an I/O read or write command during the PCI address cycle. For writes, data is loaded into the write FIFO and READYo# returned to the Local bus. For reads, PCI 9080 holds off READYo# while gathering an Lword from the PCI bus. When the I/O remap select bit is set to a value of 1, these PCI address bits [31:16] are forced to a value of 0 (refer to Table 4-43[13]). 3.6.1.6 CFG (PCI Configuration Type 0 or Type 1 Cycles) If the Configuration Enable bit is set, a CFG access is made to the PCI bus. In addition to enabling the configuration (bit 31) of (PCI:2Ch)(LOC:ACh) (refer to Table 4-44[31]), the user must provide all register information. The register number (bits [7:2]) or the device number (bits [15:11]) must be modified and a new CFT read/write cycle must be performed before other registers or devices can be accessed. If the PCI Configuration Address Register selects a Type 0 command, bits [10:0] from the register are copied to address bits [10:0]. Bits [15:11] (“device number”) are translated into a single bit being set in PCI address bits [31:11]. PCI address bits [31:11] can be used as a device select. For a Type 1 command, bits [23:0] are copied from the register to bits [23:0] of the PCI address. PCI address bits [31:24] are 0. A configuration read or write command code is output with the address during the PCI address cycle (refer to Table 4-44). For writes, local data is loaded into the write FIFO and READYo# is returned. For reads, PCI 9080 holds off READYo# while gathering an Lword from the PCI bus. Example 1—To perform a Type 0 configuration cycle to PCI device on AD[21]. 1. PCI 9080 must be configured to allow Direct Master access to the PCI buses. PCI 9080 must also be set to respond to I/O space accesses. These bits must be set in (LOC:04h): • Field 0 = I/O Space = 1 • Field 2 = Master Enable = 1 2. Direct Master Range is selected by the board designer. For this example, use a range of 1 MB: • 1 MB = 2 20 = 000FFFFFh Value to program into the range register is the inverse of 000FFFFFh, which is FFF00000h: • (LOC:9Ch) = FFF00000h 3. Local Base Address for Direct Master to PCI IO/CFG is determined by the board designer. For this example, use 40000000h: • (LOC:A4h) = 40000000h 4. PCI Address (Remap) for Direct Master to PCI Memory Register must enable Direct Master I/O access. This bit must be set in (LOC:A8h): • Field 1 = Direct Master I/O Access Enable = 1 5. PCI must know which PCI device and PCI configuration register the PCI configuration cycle is accessing. For this example, access the PCI device on AD[21]. Also access the PCI Base Address 0 for Memory Mapped Configuration Register (PCI:10h). (PCI:10h) is the fourth register, counting from 0 (use Table 4-5, “PCI Configuration Registers,” for reference). These bits must be set in (LOC:ACh): • Fields 1:0 = Configuration Type 0 = 00b • Fields 7:2 = Register number = The fourth register, and therefore must program a 4 into this field, beginning with bit 2 = 000100b • Fields 10:8 = Function Number = 000b • Fields 15:11 = Device Number = n-11, where n is the value in AD[n]=21-11 = 10 = 01010b • Fields 23:16 = Bus Number = 00000000b • Field 31 = Configuration Enable = 1 |
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