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PCI9060ES Datasheet(PDF) 66 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 66 Page - List of Unclassifed Manufacturers |
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66 / 192 page ![]() SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 57 Version 1.02 4.3.5 (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register Table 4-14. (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register Field Description Read Write Value after Reset 7:0 Register Level Programming Interface. 00h = Queue Ports at 40h and 44h. 01h = Queue Ports at 40h and 44h, and Int Status and Int Mask at 30h and 34h, respectively. Yes Local/ Serial EEPROM 00 15:8 Subclass Code. 80h = Other Bridge Device, 00h = I2O Device. Yes Local/ Serial EEPROM 80h 23:16 Base Class Code. 06h = Bridge Device, 0Eh = I2O controller. Yes Local/ Serial EEPROM 06h 4.3.6 (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register Table 4-15. (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register Field Description Read Write Value after Reset 7:0 System cache line size in units of 32-bit words. Yes Yes 0 4.3.7 (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register Table 4-16. (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register Field Description Read Write Value after Reset 7:0 PCI Latency Timer. Units of PCI bus clocks that specify the amount of time the PCI 9080, as a bus master, can burst data on the PCI bus. Yes Yes 0 4.3.8 (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register Table 4-17. (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register Field Description Read Write Value after Reset 6:0 Configuration Layout Type. Specifies the layout of bits 10h through 3Fh in configuration space. Only one encoding 0 is defined. All other encodings are reserved. Yes Local 0 7 Header Type. Value of 1 indicates multiple functions. Value of 0 indicates a single function. Yes Local 0 |
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