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PCI9060ES Datasheet(PDF) 41 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 41 Page - List of Unclassifed Manufacturers |
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41 / 192 page  SECTION 3 PCI 9080 FUNCTIONAL DESCRIPTION ©PLX Technology, Inc., 1997 Page 32 Version 1.02 3.7.3.2 PCI to Local Bus DMA Transfer • ! "#$ % & & ' ! () ! ! ( ! * ) • • • + , • • ! " - ( . & ( $ & ! • • ! " - ( . & ( $ & ! "#$/ 01/ 2& 2& ! ! 01 ! & '! () ! ! ( ) ! ! ! ) • * ( &3 ( ( ! # & ! ( ) ( 3 & ! • * ( &3 ( ( ! # & ! ( ) ( 3 & ! Figure 3-20. PCI to Local Bus DMA Data Transfer Operation 3.7.3.3 Unaligned Transfers For unaligned local to PCI transfers, PCI 9080 reads a partial Lword from the local bus. It continues to read Lwords from the local bus. Lwords are assembled, aligned to the PCI bus address and loaded into the FIFO. For PCI to local transfers, Lwords are read from the PCI bus and loaded into the FIFO. On the local side, the Lwords are assembled from the FIFO, aligned to the local bus address and written to the local bus. On both the local and PCI buses, the byte enables for writes determine LA[1:0] for the start of a transfer. For the last transfer, the byte enables specify the bytes to be written. All reads are Lwords. 3.7.4 Demand Mode DMA DMA Mode Register bit 15 (BLAST mode for demand mode DMA), determines the number of Lwords transferred after a DMA controllers DREQ[1:0]# input is de-asserted. If BLAST# output is not required for the last Lword of the DMA transfer (bit 15 = 1), the DMA controller releases the data bus after it receives an external READYi# or the internal wait state counter decrements to a value of 0 for the current Lword. If DMA controller is currently bursting data, which is not the last data phase for the burst, BLAST# output will not be asserted. If BLAST# output is required for the last Lword of the DMA transfer (bit 15 = 0), the DMA controller transfers one or two Lwords. If DREQ[1:0]# is de-asserted during the address phase of the first transfer in a PCI 9080 local bus ownership (ADS#, LHOLDA asserted), the DMA controller completes the current Lword. If DREQ[1:0]# is de-asserted during any phase other than the address phase of the first transfer in a PCI 9080 local bus ownership, the DMA controller completes the current Lword, and one additional Lword (this allows BLAST# output to be asserted during the final Lword). If DMA FIFO is full/empty after the data phase in which |
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