PCI9060ES datasheet(46/192 Pages) ETC

46 / 192 page

SECTION 3

PCI 9080

FUNCTIONAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 37

Version 1.02

A Done Status Bit in the Control/Status Register can be

used to determine whether the interrupt is

•

A done interrupt

•

The result of a transfer for a descriptor in a chain

that is not yet complete

Mode Register of a channel enables a done interrupt. In

chaining mode, a bit in the Next Descriptor Pointer

specifies whether to generate an interrupt at the end of

the transfer for the current descriptor.

A DMA channel interrupt is cleared by writing a 1 to the

Clear Interrupt bit in the DMA Command/Status Register

(refer to Table 4-72[3] and Table 4-73[3]).

3.12.3 PCI SERR# (PCI NMI)

PCI 9080 generates an SERR# pulse if parity checking

is enabled in the PCI Command Register and it detects

an address parity error or the Generate SERR# Bit in the

Interrupt Control/Status Register (refer to Table 4-58) is

0 and a 1 is written.

SERR# output can be enabled or disabled with PCI

Command Register.

3.12.4 Local LSERR# (Local NMI)

LSERR# interrupt output is asserted if the following

occurs:

•

PCI Bus Target Abort or Master Abort status bit is

set in the PCI Status configuration register

•

Parity error status bit is set in the PCI Status

configuration register

•

Messaging outbound free queue overflows

If parity error checking is enabled in the PCI Command

Status bit in the PCI Status configuration register (refer

to Table 4-12) if it detects one of the following:

•

Parity error during a PCI 9080 master read

•

PCI bus signal PERR# being asserted during a PCI

9080 master write

PCI 9080 sets a parity error bit in the PCI Status

configuration register (refer to Table 4-12) if it detects

one of the following:

•

Data parity error during a PCI 9080 master read

•

Data parity error during a slave write access to the

PCI 9080

•

Address parity error

The PCI 9080 Interrupt Control/Status Register (refer to

Table 4-58) can be used to individually enable or disable

LSERR# for an abort or parity error. LSERR# is a level

output that remains asserted as long as the Abort or

Parity Error Status bits are set.

3.13 I20 COMPATIBLE MESSAGE UNIT

Messaging Unit supplies two paths for messages, two

inbound FIFOs to receive messages from the primary

PCI bus and two outbound FIFOs to pass messages to

the

primary

PCI

bus.

Refer

I2O Architecture

Specification v1.5 for details.

Figure 3-22 and Figure 3-23 illustrate information about

the I20 architecture.

$ , - $

Figure 3-22. I2O System Architecture

Figure 3-23. I2O Software Architecture

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