PCI9060ES datasheet(74/192 Pages) ETC

74 / 192 page

SECTION 4

PCI 9080

REGISTERS

©PLX Technology, Inc., 1997

Page 65

Version 1.02

4.4.4 (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register

Table 4-36. (BIGEND; PCI:0Ch, LOC:8Ch) Big/Little Endian Descriptor Register

Field

Description

Read

Write

Value after Reset

Configuration Register Big Endian Mode. Value of 1 specifies use of Big Endian

data ordering for local accesses to the configuration registers. Value of 0 specifies

Little Endian ordering. Big Endian mode can be specified for configuration register

accesses by asserting the BIGEND# pin during the address phase of the access.

Yes

Direct Master Big Endian Mode. Value of 1 specifies use of Big Endian data

ordering for Direct Master accesses. Value of 0 specifies Little Endian ordering. Big

Endian mode can be specified for Direct Master accesses by asserting the

BIGEND# input pin during the address phase of the access.

Yes

Direct Slave Address Space 0 Big Endian Mode. Value of 1 specifies use of Big

Endian data ordering for Direct Slave accesses to Local Address space 0. Value of

0 specifies Little Endian ordering.

Yes

Direct Slave Address Expansion ROM 0 Big Endian Mode. Value of 1 specifies use

of Big Endian data ordering for Direct Slave accesses to Expansion ROM. Value of

0 specifies Little Endian ordering.

Yes

Big Endian Byte Lane Mode. Value of 1 specifies that in Big Endian mode, use byte

lanes 31:16 for a 16 bit local bus and byte lanes 31:24 for an 8 bit local bus. Value

of 0 specifies that in Big Endian mode, byte lanes 15:0 be used for a 16 bit local

bus and byte lanes 7:0 for an 8 bit local bus.

Yes

Direct Slave Address Space 1 Big Endian Mode. Value of 1 specifies use of Big

Endian data ordering for Direct Slave accesses to local Address Space 1. Value of

0 specifies Little Endian ordering.

Yes

DMA Channel 1 Big Endian Mode. Value of 1 specifies use of Big Endian data

ordering for DMA Channel 1 accesses to the local Address Space. Value of 0

specifies Little Endian ordering.

Yes

DMA Channel 0 Big Endian Mode. Value of 1 specifies use of Big Endian data

ordering for DMA Channel 0 accesses to the Local Address space. Value of 0

specifies Little Endian ordering.

Yes

31:8

Reserved.

Yes

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