PCI9060ES datasheet(14/192 Pages) ETC

14 / 192 page

SECTION 1

PCI 9080

GENERAL DESCRIPTION

©PLX Technology, Inc., 1997

Page 5

Version 1.02

1.4 COMPARISON OF PCI 9060, PCI 9060ES, PCI 9060SD, AND PCI 9080

Table 1-3. Comparison of the PCI 9060, PCI 9060ES, PCI 9060SD, and PCI 9080

Feature

PCI 9060

PCI 9060ES

PCI 9060SD

PCI 9080

Number of DMA Channel(s)

Local Address Spaces

Direct Master Mode

Yes

Mailbox Registers

Eight 32 bit

Four 32 bit

Eight 32 bit

Doorbell Registers

Two 32 bit

Two 8 bit

Two 32 bit

FIFOs

FIFO Depth—Direct Slave Write, Direct Master

Write, DMA 0 Read and DMA 0 Write

8 Lwords

(32 bytes)

16 Lwords

(64 bytes)

16 Lwords

(64 bytes)

32 Lwords

(128 bytes)

FIFO Depth —Direct Slave Read, Direct Master

Read, DMA 1 Read and DMA 1 Write

8 Lwords

(32 bytes)

16 Lwords

(64 bytes)

16 Lwords

(64 bytes)

16 Lwords

(64 bytes)

LLOCKo# Pin for Lock Cycles

Yes

WAITI# Pin for Wait State Generation

Yes

BPCLKo Pin; Buffered PCI Clock

Yes

DREQ# and DACK# Pins for Demand Mode

DMA Support

Yes

(Channel 1 only)

Yes

—

Identical except

9060ES has no

DMA registers and

Tables 25, 26, and 43

were added

Identical, except

9060SD has one

DMA register and

Tables 4-29 and 4-30

were added

Identical except PCI

9080 has additional

I2O related registers

and 30h, 34h, 40h,

and 44h were

remapped

Pin Out

Note:

PCI 9080 includes all changes made

for PCI 9060, PCI 9060ES, and PCI 9060SD.

—

Signals deleted:

DREQ0# (pin 29)

DACK0# (pin 30)

Input signals added:

WAITI# (pin 6)

BIGEND# (pin 48)

Output signals added:

BPCLKo (pin 168)

LLOCKo# (pin 7)

Signals deleted:

BREQ (pin 21)

DMPAF# (pin 8)

DREQ0# (pin 29)

DACK0# (pin 30)

BTERMo# (pin 28)

Input signals added:

WAITI# (pin 6)

BIGEND# (pin 48)

EOT0# (pin 164 in

C mode, Pin 5 in

J and S modes)

Output signals added:

BPCLKo (pin 168)

LLOCKo# (pin 7)

Input signal added:

EOT1# (pin 163)

Signal changed:

EESEL (pin 175)

Big/Little Endian Conversion

Yes

Spec. 2.1 Deferred Reads

Yes

Programmable Prefetch Counter

Yes

Write and Invalidate Cycle

Yes

Additional Device and Vendor ID Register

Yes

I2O Messaging Unit

Yes

3.3 V PCI Bus Signaling

Yes

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