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PCI9060ES Datasheet(PDF) 63 Page - List of Unclassifed Manufacturers |
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PCI9060ES Datasheet(HTML) 63 Page - List of Unclassifed Manufacturers |
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63 / 192 page  SECTION 4 PCI 9080 REGISTERS ©PLX Technology, Inc., 1997 Page 54 Version 1.02 4.2.5 Messaging Queue Registers Table 4-9. Messaging Queue Registers PCI (Offset from Base Address) Local Access (Offset from Chip Select Address) To ensure software compatibility with other versions of the PCI 9080 family and to ensure compatibility with future enhancements, write a zero to all unused bits. 31 0 PCI/Local Writable Serial EEPROM Writable 30h B0h Outbound Post Queue Interrupt Status N N 34h B4h Outbound Post Queue Interrupt Mask Y N 40h — Inbound Queue Port PCI N 44h — Outbound Queue Port PCI N C0h 140h Messaging Unit Configuration Register Y N C4h 144h Queue Base Address Register Y N C8h 148h Inbound Free Head Pointer Register Y N CCh 14Ch Inbound Free Tail Pointer Register Y N D0h 150h Inbound Post Head Pointer Register Y N D4h 154h Inbound Post Tail Pointer Register Y N D8h 158h Outbound Free Head Pointer Register Y N DCh 15Ch Outbound Free Tail Pointer Register Y N E0h 160h Outbound Post Head Pointer Register Y N E4h 164h Outbound Post Tail Pointer Register Y N E8h 168h Queue Status/Control Register Y N Notes: When I2O messaging is enabled (bit 0 of QSR register = 1), a PCI Master (Host or another IOP) uses the Inbound Queue Port to read MFAs from the Inbound Free List FIFO and to write MFAs to the Inbound Post List FIFO. It uses the Outbound Queue Port to read MFAs from the Outbound Post List FIFO and to write MFAs to the Outbound Free List FIFO. Each Inbound Message Frame Address (MFA) is specified by I2O as the offset from the PCI Base Address 0 (programmed in register PCIBAR0 at offset 10H) to the start of the message frame. This means that all inbound message frames should reside in PCI Base Address 0 memory space. Each Outbound Message Frame Address (MFA) is specified by I2O as the offset from system address 0x00000000h. So the Outbound MFA is the physical 32-bit address of the frame in shared PCI system memory. Inbound and Outbound Queues may reside in Local Address Space 0 or 1 by programming the QSR register. They need not be in shared memory. |
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