PCI9060ES datasheet(115/192 Pages) ETC

115 / 192 page

SECTION 8

PCI 9080

TIMING DIAGRAMS

©PLX Technology, Inc., 1997

Page 106

Version 1.02

8. TIMING DIAGRAMS

The PCI 9080 operates in three modes, selected through mode pins, corresponding to three bus types—C, J, and S.

Timing Diagrams are provided for the three operating modes. For some functions, a timing diagram may only be provided

for one mode of operation. Even though a different mode is used, the timing diagram can be used to determine

functionality.

8.1 LIST OF TIMING DIAGRAMS

Initialization

Timing Diagram 8-1. (C, J Modes) PCI RST# Asserting Local Output LRESETo#

Timing Diagram 8-2. (S Mode) Two Phase Clock Synchronization Using LRESETo#

Timing Diagram 8-3. PCI 9080 Local Bus Arbitration

Timing Diagram 8-4. PCI 9080 1K Serial EEPROM PCI Initialization

Timing Diagram 8-5. Local Interrupt (LINTi#) Input Asserting PCI Output INTA#

C Mode Direct Slave

Timing Diagram 8-6. (C Mode) PCI Configuration Write to PCI 9080 PCI Configuration Register

Timing Diagram 8-7. (C Mode) PCI Configuration Read to PCI 9080 PCI Configuration Register

Timing Diagram 8-8. (C Mode) PCI Configuration Write to PCI 9080 Local Configuration Register

Timing Diagram 8-9. (C Mode) PCI Configuration Read to PCI 9080 Local Configuration Register

Timing Diagram 8-10. (C Mode) Direct Slave Single Cycle Read

Timing Diagram 8-11. (C Mode) Direct Slave Single Cycle Write

Timing Diagram 8-12. (C Mode) PCI 9080 DMA or Direct Slave Burst Read from Local Bus, Bterm Enabled

Timing Diagram 8-13. (C Mode) DMA or Direct Slave PCI 9080 Burst Write to Local Bus, Bterm Enabled

Timing Diagram 8-14. (C Mode) Direct Slave PCI to Local Burst Read, Bterm Disabled

Timing Diagram 8-15. (C Mode) PCI 9080 DMA or Direct Slave Burst Write, Bterm Disabled

Timing Diagram 8-16. (C Mode) Direct Slave Read with Prefetch Counter Set to 5

Timing Diagram 8-17. (C Mode) Direct Slave or DMA Burst Write to 32 bit local bus Suspended by BREQ Input

Timing Diagram 8-18. (C Mode) Direct Slave Burst Read of Five Lwords with One Wait State

Timing Diagram 8-19. (C Mode) Direct Slave Burst of Five Lwords with One Wait State

Timing Diagram 8-20. (C Mode) Direct Slave Read 2.1 Spec

Timing Diagram 8-21. (C Mode) Direct Slave Read No Flush Mode (Read Ahead Mode)

Timing Diagram 8-22. (C Mode) Direct Slave Read of Two Lwords from 8-Bit Bus

Timing Diagram 8-23. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 8 Bit Local Bus

Timing Diagram 8-24. (C Mode) Direct Slave Read of Two Lwords from 16-Bit Bus

Timing Diagram 8-25. (C Mode) PCI 9080 DMA or Direct Slave Two Lword Burst Write to 16 Bit Local Bus

Timing Diagram 8-26. (C Mode) Direct Slave Read of Two Lwords from 8 Bit I/O Local Bus

Timing Diagram 8-27. (C Mode) Direct Slave Write of Two Lwords to 8 Bit I/O Local Bus

Timing Diagram 8-28. (C Mode) Direct Slave in BIGEND Local Bus with BIGEND# Input or Internal Register Setting

Timing Diagram 8-29. (C Mode) Locked Direct Slave Read Followed by Write and Release (LLOCKo#)

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